1*d7964de8SJohnson Wang /* SPDX-License-Identifier: GPL-2.0-only */ 2*d7964de8SJohnson Wang /* 3*d7964de8SJohnson Wang * Copyright (c) 2022 MediaTek Inc. 4*d7964de8SJohnson Wang * Author: Edward-JW Yang <edward-jw.yang@mediatek.com> 5*d7964de8SJohnson Wang */ 6*d7964de8SJohnson Wang 7*d7964de8SJohnson Wang #ifndef __CLK_PLLFH_H 8*d7964de8SJohnson Wang #define __CLK_PLLFH_H 9*d7964de8SJohnson Wang 10*d7964de8SJohnson Wang #include "clk-pll.h" 11*d7964de8SJohnson Wang 12*d7964de8SJohnson Wang struct fh_pll_state { 13*d7964de8SJohnson Wang void __iomem *base; 14*d7964de8SJohnson Wang u32 fh_enable; 15*d7964de8SJohnson Wang u32 ssc_rate; 16*d7964de8SJohnson Wang }; 17*d7964de8SJohnson Wang 18*d7964de8SJohnson Wang struct fh_pll_data { 19*d7964de8SJohnson Wang int pll_id; 20*d7964de8SJohnson Wang int fh_id; 21*d7964de8SJohnson Wang u32 fhx_offset; 22*d7964de8SJohnson Wang u32 dds_mask; 23*d7964de8SJohnson Wang u32 slope0_value; 24*d7964de8SJohnson Wang u32 slope1_value; 25*d7964de8SJohnson Wang u32 sfstrx_en; 26*d7964de8SJohnson Wang u32 frddsx_en; 27*d7964de8SJohnson Wang u32 fhctlx_en; 28*d7964de8SJohnson Wang u32 tgl_org; 29*d7964de8SJohnson Wang u32 dvfs_tri; 30*d7964de8SJohnson Wang u32 pcwchg; 31*d7964de8SJohnson Wang u32 dt_val; 32*d7964de8SJohnson Wang u32 df_val; 33*d7964de8SJohnson Wang u32 updnlmt_shft; 34*d7964de8SJohnson Wang u32 msk_frddsx_dys; 35*d7964de8SJohnson Wang u32 msk_frddsx_dts; 36*d7964de8SJohnson Wang }; 37*d7964de8SJohnson Wang 38*d7964de8SJohnson Wang struct mtk_pllfh_data { 39*d7964de8SJohnson Wang struct fh_pll_state state; 40*d7964de8SJohnson Wang const struct fh_pll_data data; 41*d7964de8SJohnson Wang }; 42*d7964de8SJohnson Wang 43*d7964de8SJohnson Wang struct fh_pll_regs { 44*d7964de8SJohnson Wang void __iomem *reg_hp_en; 45*d7964de8SJohnson Wang void __iomem *reg_clk_con; 46*d7964de8SJohnson Wang void __iomem *reg_rst_con; 47*d7964de8SJohnson Wang void __iomem *reg_slope0; 48*d7964de8SJohnson Wang void __iomem *reg_slope1; 49*d7964de8SJohnson Wang void __iomem *reg_cfg; 50*d7964de8SJohnson Wang void __iomem *reg_updnlmt; 51*d7964de8SJohnson Wang void __iomem *reg_dds; 52*d7964de8SJohnson Wang void __iomem *reg_dvfs; 53*d7964de8SJohnson Wang void __iomem *reg_mon; 54*d7964de8SJohnson Wang }; 55*d7964de8SJohnson Wang 56*d7964de8SJohnson Wang struct mtk_fh { 57*d7964de8SJohnson Wang struct mtk_clk_pll clk_pll; 58*d7964de8SJohnson Wang struct fh_pll_regs regs; 59*d7964de8SJohnson Wang struct mtk_pllfh_data *pllfh_data; 60*d7964de8SJohnson Wang const struct fh_operation *ops; 61*d7964de8SJohnson Wang spinlock_t *lock; 62*d7964de8SJohnson Wang }; 63*d7964de8SJohnson Wang 64*d7964de8SJohnson Wang struct fh_operation { 65*d7964de8SJohnson Wang int (*hopping)(struct mtk_fh *fh, unsigned int new_dds, 66*d7964de8SJohnson Wang unsigned int postdiv); 67*d7964de8SJohnson Wang int (*ssc_enable)(struct mtk_fh *fh, u32 rate); 68*d7964de8SJohnson Wang }; 69*d7964de8SJohnson Wang 70*d7964de8SJohnson Wang int mtk_clk_register_pllfhs(struct device_node *node, 71*d7964de8SJohnson Wang const struct mtk_pll_data *plls, int num_plls, 72*d7964de8SJohnson Wang struct mtk_pllfh_data *pllfhs, int num_pllfhs, 73*d7964de8SJohnson Wang struct clk_hw_onecell_data *clk_data); 74*d7964de8SJohnson Wang 75*d7964de8SJohnson Wang void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls, 76*d7964de8SJohnson Wang struct mtk_pllfh_data *pllfhs, int num_fhs, 77*d7964de8SJohnson Wang struct clk_hw_onecell_data *clk_data); 78*d7964de8SJohnson Wang 79*d7964de8SJohnson Wang void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs, 80*d7964de8SJohnson Wang int num_pllfhs); 81*d7964de8SJohnson Wang 82*d7964de8SJohnson Wang #endif /* __CLK_PLLFH_H */ 83