1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Edward-JW Yang <edward-jw.yang@mediatek.com> 5 */ 6 7 #include <linux/of.h> 8 #include <linux/of_address.h> 9 #include <linux/io.h> 10 #include <linux/slab.h> 11 #include <linux/clkdev.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 15 #include "clk-mtk.h" 16 #include "clk-pllfh.h" 17 #include "clk-fhctl.h" 18 19 static DEFINE_SPINLOCK(pllfh_lock); 20 21 inline struct mtk_fh *to_mtk_fh(struct clk_hw *hw) 22 { 23 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 24 25 return container_of(pll, struct mtk_fh, clk_pll); 26 } 27 28 static int mtk_fhctl_set_rate(struct clk_hw *hw, unsigned long rate, 29 unsigned long parent_rate) 30 { 31 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 32 struct mtk_fh *fh = to_mtk_fh(hw); 33 u32 pcw = 0; 34 u32 postdiv; 35 36 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); 37 38 return fh->ops->hopping(fh, pcw, postdiv); 39 } 40 41 static const struct clk_ops mtk_pllfh_ops = { 42 .is_prepared = mtk_pll_is_prepared, 43 .prepare = mtk_pll_prepare, 44 .unprepare = mtk_pll_unprepare, 45 .recalc_rate = mtk_pll_recalc_rate, 46 .determine_rate = mtk_pll_determine_rate, 47 .set_rate = mtk_fhctl_set_rate, 48 }; 49 50 static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_pllfh_data *pllfhs, 51 int num_fhs, int pll_id) 52 { 53 int i; 54 55 for (i = 0; i < num_fhs; i++) 56 if (pllfhs[i].data.pll_id == pll_id) 57 return &pllfhs[i]; 58 59 return NULL; 60 } 61 62 void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs, 63 int num_fhs) 64 { 65 void __iomem *base; 66 struct device_node *node; 67 u32 num_clocks, pll_id, ssc_rate; 68 int offset, i; 69 70 node = of_find_compatible_node(NULL, NULL, compatible_node); 71 if (!node) { 72 pr_warn("cannot find \"%s\"\n", compatible_node); 73 return; 74 } 75 76 base = of_iomap(node, 0); 77 if (!base) { 78 pr_err("%s(): ioremap failed\n", __func__); 79 goto out_node_put; 80 } 81 82 num_clocks = of_clk_get_parent_count(node); 83 if (!num_clocks) { 84 pr_err("%s(): failed to get clocks property\n", __func__); 85 goto err; 86 } 87 88 for (i = 0; i < num_clocks; i++) { 89 struct mtk_pllfh_data *pllfh; 90 91 offset = i * 2; 92 93 of_property_read_u32_index(node, "clocks", offset + 1, &pll_id); 94 of_property_read_u32_index(node, 95 "mediatek,hopping-ssc-percent", 96 i, &ssc_rate); 97 98 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll_id); 99 if (!pllfh) 100 continue; 101 102 pllfh->state.fh_enable = 1; 103 pllfh->state.ssc_rate = ssc_rate; 104 pllfh->state.base = base; 105 } 106 107 out_node_put: 108 of_node_put(node); 109 return; 110 err: 111 iounmap(base); 112 goto out_node_put; 113 } 114 EXPORT_SYMBOL_GPL(fhctl_parse_dt); 115 116 static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data) 117 { 118 struct fh_pll_regs *regs = &fh->regs; 119 const struct fhctl_offset *offset; 120 void __iomem *base = pllfh_data->state.base; 121 void __iomem *fhx_base = base + pllfh_data->data.fhx_offset; 122 123 offset = fhctl_get_offset_table(pllfh_data->data.fh_ver); 124 if (IS_ERR(offset)) 125 return PTR_ERR(offset); 126 127 regs->reg_hp_en = base + offset->offset_hp_en; 128 regs->reg_clk_con = base + offset->offset_clk_con; 129 regs->reg_rst_con = base + offset->offset_rst_con; 130 regs->reg_slope0 = base + offset->offset_slope0; 131 regs->reg_slope1 = base + offset->offset_slope1; 132 133 regs->reg_cfg = fhx_base + offset->offset_cfg; 134 regs->reg_updnlmt = fhx_base + offset->offset_updnlmt; 135 regs->reg_dds = fhx_base + offset->offset_dds; 136 regs->reg_dvfs = fhx_base + offset->offset_dvfs; 137 regs->reg_mon = fhx_base + offset->offset_mon; 138 139 fh->pllfh_data = pllfh_data; 140 fh->lock = &pllfh_lock; 141 142 fh->ops = fhctl_get_ops(); 143 144 return 0; 145 } 146 147 static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh) 148 { 149 return pllfh && (pllfh->state.fh_enable == 1); 150 } 151 152 static struct clk_hw * 153 mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_data, 154 struct mtk_pllfh_data *pllfh_data, void __iomem *base) 155 { 156 struct clk_hw *hw; 157 struct mtk_fh *fh; 158 int ret; 159 160 fh = kzalloc_obj(*fh); 161 if (!fh) 162 return ERR_PTR(-ENOMEM); 163 164 ret = pllfh_init(fh, pllfh_data); 165 if (ret) { 166 hw = ERR_PTR(ret); 167 goto out; 168 } 169 170 fh->clk_pll.dev = dev; 171 172 hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, 173 &mtk_pllfh_ops); 174 175 if (IS_ERR(hw)) 176 goto out; 177 178 fhctl_hw_init(fh); 179 180 out: 181 if (IS_ERR(hw)) 182 kfree(fh); 183 184 return hw; 185 } 186 187 static void mtk_clk_unregister_pllfh(struct clk_hw *hw) 188 { 189 struct mtk_fh *fh; 190 191 if (!hw) 192 return; 193 194 fh = to_mtk_fh(hw); 195 196 clk_hw_unregister(hw); 197 kfree(fh); 198 } 199 200 int mtk_clk_register_pllfhs(struct device *dev, 201 const struct mtk_pll_data *plls, int num_plls, 202 struct mtk_pllfh_data *pllfhs, int num_fhs, 203 struct clk_hw_onecell_data *clk_data) 204 { 205 void __iomem *base; 206 int i; 207 struct clk_hw *hw; 208 209 base = of_iomap(dev->of_node, 0); 210 if (!base) { 211 pr_err("%s(): ioremap failed\n", __func__); 212 return -EINVAL; 213 } 214 215 for (i = 0; i < num_plls; i++) { 216 const struct mtk_pll_data *pll = &plls[i]; 217 struct mtk_pllfh_data *pllfh; 218 bool use_fhctl; 219 220 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id); 221 use_fhctl = fhctl_is_supported_and_enabled(pllfh); 222 223 if (use_fhctl) 224 hw = mtk_clk_register_pllfh(dev, pll, pllfh, base); 225 else 226 hw = mtk_clk_register_pll(dev, pll, base); 227 228 if (IS_ERR(hw)) { 229 pr_err("Failed to register %s clk %s: %ld\n", 230 use_fhctl ? "fhpll" : "pll", pll->name, 231 PTR_ERR(hw)); 232 goto err; 233 } 234 235 clk_data->hws[pll->id] = hw; 236 } 237 238 return 0; 239 240 err: 241 while (--i >= 0) { 242 const struct mtk_pll_data *pll = &plls[i]; 243 struct mtk_pllfh_data *pllfh; 244 bool use_fhctl; 245 246 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id); 247 use_fhctl = fhctl_is_supported_and_enabled(pllfh); 248 249 if (use_fhctl) 250 mtk_clk_unregister_pllfh(clk_data->hws[pll->id]); 251 else 252 mtk_clk_unregister_pll(clk_data->hws[pll->id]); 253 254 clk_data->hws[pll->id] = ERR_PTR(-ENOENT); 255 } 256 257 iounmap(base); 258 259 return PTR_ERR(hw); 260 } 261 EXPORT_SYMBOL_GPL(mtk_clk_register_pllfhs); 262 263 void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls, 264 struct mtk_pllfh_data *pllfhs, int num_fhs, 265 struct clk_hw_onecell_data *clk_data) 266 { 267 void __iomem *base = NULL, *fhctl_base = NULL; 268 int i; 269 270 if (!clk_data) 271 return; 272 273 for (i = num_plls; i > 0; i--) { 274 const struct mtk_pll_data *pll = &plls[i - 1]; 275 struct mtk_pllfh_data *pllfh; 276 bool use_fhctl; 277 278 if (IS_ERR_OR_NULL(clk_data->hws[pll->id])) 279 continue; 280 281 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id); 282 use_fhctl = fhctl_is_supported_and_enabled(pllfh); 283 284 if (use_fhctl) { 285 fhctl_base = pllfh->state.base; 286 mtk_clk_unregister_pllfh(clk_data->hws[pll->id]); 287 } else { 288 base = mtk_clk_pll_get_base(clk_data->hws[pll->id], 289 pll); 290 mtk_clk_unregister_pll(clk_data->hws[pll->id]); 291 } 292 293 clk_data->hws[pll->id] = ERR_PTR(-ENOENT); 294 } 295 296 if (fhctl_base) 297 iounmap(fhctl_base); 298 299 iounmap(base); 300 } 301 EXPORT_SYMBOL_GPL(mtk_clk_unregister_pllfhs); 302