1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #ifndef __DRV_CLK_MTK_PLL_H 8 #define __DRV_CLK_MTK_PLL_H 9 10 #include <linux/clk-provider.h> 11 #include <linux/types.h> 12 13 struct device; 14 15 struct mtk_pll_div_table { 16 u32 div; 17 unsigned long freq; 18 }; 19 20 #define HAVE_RST_BAR BIT(0) 21 #define PLL_AO BIT(1) 22 #define PLL_PARENT_EN BIT(2) 23 #define POSTDIV_MASK GENMASK(2, 0) 24 25 struct mtk_pll_data { 26 int id; 27 const char *name; 28 u32 reg; 29 u32 pwr_reg; 30 u32 en_mask; 31 u32 fenc_sta_ofs; 32 u32 pd_reg; 33 u32 tuner_reg; 34 u32 tuner_en_reg; 35 u8 tuner_en_bit; 36 int pd_shift; 37 unsigned int flags; 38 const struct clk_ops *ops; 39 u32 rst_bar_mask; 40 unsigned long fmin; 41 unsigned long fmax; 42 int pcwbits; 43 int pcwibits; 44 u32 pcw_reg; 45 int pcw_shift; 46 u32 pcw_chg_reg; 47 const struct mtk_pll_div_table *div_table; 48 const char *parent_name; 49 u32 en_reg; 50 u32 en_set_reg; 51 u32 en_clr_reg; 52 u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ 53 u8 pcw_chg_bit; 54 u8 fenc_sta_bit; 55 }; 56 57 /* 58 * MediaTek PLLs are configured through their pcw value. The pcw value describes 59 * a divider in the PLL feedback loop which consists of 7 bits for the integer 60 * part and the remaining bits (if present) for the fractional part. Also they 61 * have a 3 bit power-of-two post divider. 62 */ 63 64 struct mtk_clk_pll { 65 struct device *dev; 66 struct clk_hw hw; 67 void __iomem *base_addr; 68 void __iomem *pd_addr; 69 void __iomem *pwr_addr; 70 void __iomem *tuner_addr; 71 void __iomem *tuner_en_addr; 72 void __iomem *pcw_addr; 73 void __iomem *pcw_chg_addr; 74 void __iomem *en_addr; 75 void __iomem *en_set_addr; 76 void __iomem *en_clr_addr; 77 void __iomem *fenc_addr; 78 const struct mtk_pll_data *data; 79 }; 80 81 int mtk_clk_register_plls(struct device *dev, const struct mtk_pll_data *plls, 82 int num_plls, struct clk_hw_onecell_data *clk_data); 83 84 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, 85 struct clk_hw_onecell_data *clk_data); 86 87 extern const struct clk_ops mtk_pll_ops; 88 extern const struct clk_ops mtk_pll_fenc_clr_set_ops; 89 90 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) 91 { 92 return container_of(hw, struct mtk_clk_pll, hw); 93 } 94 95 int mtk_pll_is_prepared(struct clk_hw *hw); 96 97 int mtk_pll_prepare(struct clk_hw *hw); 98 99 void mtk_pll_unprepare(struct clk_hw *hw); 100 101 unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); 102 103 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, 104 u32 freq, u32 fin); 105 int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 106 unsigned long parent_rate); 107 int mtk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req); 108 109 struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, 110 const struct mtk_pll_data *data, 111 void __iomem *base, 112 const struct clk_ops *pll_ops); 113 struct clk_hw *mtk_clk_register_pll(struct device *dev, 114 const struct mtk_pll_data *data, 115 void __iomem *base); 116 void mtk_clk_unregister_pll(struct clk_hw *hw); 117 118 __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw, 119 const struct mtk_pll_data *data); 120 121 #endif /* __DRV_CLK_MTK_PLL_H */ 122