1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/container_of.h> 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/slab.h> 16 17 #include "clk-pll.h" 18 19 #define MHZ (1000 * 1000) 20 21 #define REG_CON0 0 22 #define REG_CON1 4 23 24 #define CON0_BASE_EN BIT(0) 25 #define CON0_PWR_ON BIT(0) 26 #define CON0_ISO_EN BIT(1) 27 #define PCW_CHG_BIT 31 28 29 #define AUDPLL_TUNER_EN BIT(31) 30 31 /* default 7 bits integer, can be overridden with pcwibits. */ 32 #define INTEGER_BITS 7 33 34 int mtk_pll_is_prepared(struct clk_hw *hw) 35 { 36 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 37 38 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; 39 } 40 41 static int mtk_pll_fenc_is_prepared(struct clk_hw *hw) 42 { 43 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 44 45 return !!(readl(pll->fenc_addr) & BIT(pll->data->fenc_sta_bit)); 46 } 47 48 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, 49 u32 pcw, int postdiv) 50 { 51 int pcwbits = pll->data->pcwbits; 52 int pcwfbits = 0; 53 int ibits; 54 u64 vco; 55 u8 c = 0; 56 57 /* The fractional part of the PLL divider. */ 58 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; 59 if (pcwbits > ibits) 60 pcwfbits = pcwbits - ibits; 61 62 vco = (u64)fin * pcw; 63 64 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) 65 c = 1; 66 67 vco >>= pcwfbits; 68 69 if (c) 70 vco++; 71 72 return ((unsigned long)vco + postdiv - 1) / postdiv; 73 } 74 75 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) 76 { 77 u32 r; 78 79 if (pll->tuner_en_addr) { 80 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); 81 writel(r, pll->tuner_en_addr); 82 } else if (pll->tuner_addr) { 83 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; 84 writel(r, pll->tuner_addr); 85 } 86 } 87 88 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) 89 { 90 u32 r; 91 92 if (pll->tuner_en_addr) { 93 r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); 94 writel(r, pll->tuner_en_addr); 95 } else if (pll->tuner_addr) { 96 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; 97 writel(r, pll->tuner_addr); 98 } 99 } 100 101 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, 102 int postdiv) 103 { 104 u32 chg, val; 105 106 /* disable tuner */ 107 __mtk_pll_tuner_disable(pll); 108 109 /* set postdiv */ 110 val = readl(pll->pd_addr); 111 val &= ~(POSTDIV_MASK << pll->data->pd_shift); 112 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; 113 114 /* postdiv and pcw need to set at the same time if on same register */ 115 if (pll->pd_addr != pll->pcw_addr) { 116 writel(val, pll->pd_addr); 117 val = readl(pll->pcw_addr); 118 } 119 120 /* set pcw */ 121 val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1, 122 pll->data->pcw_shift); 123 val |= pcw << pll->data->pcw_shift; 124 writel(val, pll->pcw_addr); 125 chg = readl(pll->pcw_chg_addr) | 126 BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT); 127 writel(chg, pll->pcw_chg_addr); 128 if (pll->tuner_addr) 129 writel(val + 1, pll->tuner_addr); 130 131 /* restore tuner_en */ 132 __mtk_pll_tuner_enable(pll); 133 134 udelay(20); 135 } 136 137 /* 138 * mtk_pll_calc_values - calculate good values for a given input frequency. 139 * @pll: The pll 140 * @pcw: The pcw value (output) 141 * @postdiv: The post divider (output) 142 * @freq: The desired target frequency 143 * @fin: The input frequency 144 * 145 */ 146 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, 147 u32 freq, u32 fin) 148 { 149 unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ); 150 const struct mtk_pll_div_table *div_table = pll->data->div_table; 151 u64 _pcw; 152 int ibits; 153 u32 val; 154 155 if (freq > pll->data->fmax) 156 freq = pll->data->fmax; 157 158 if (div_table) { 159 if (freq > div_table[0].freq) 160 freq = div_table[0].freq; 161 162 for (val = 0; div_table[val + 1].freq != 0; val++) { 163 if (freq > div_table[val + 1].freq) 164 break; 165 } 166 *postdiv = 1 << val; 167 } else { 168 for (val = 0; val < 5; val++) { 169 *postdiv = 1 << val; 170 if ((u64)freq * *postdiv >= fmin) 171 break; 172 } 173 } 174 175 /* _pcw = freq * postdiv / fin * 2^pcwfbits */ 176 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; 177 _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); 178 do_div(_pcw, fin); 179 180 *pcw = (u32)_pcw; 181 } 182 183 int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 184 unsigned long parent_rate) 185 { 186 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 187 u32 pcw = 0; 188 u32 postdiv; 189 190 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); 191 mtk_pll_set_rate_regs(pll, pcw, postdiv); 192 193 return 0; 194 } 195 196 unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 197 { 198 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 199 u32 postdiv; 200 u32 pcw; 201 202 postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; 203 postdiv = 1 << postdiv; 204 205 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; 206 pcw &= GENMASK(pll->data->pcwbits - 1, 0); 207 208 return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); 209 } 210 211 int mtk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 212 { 213 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 214 u32 pcw = 0; 215 int postdiv; 216 217 mtk_pll_calc_values(pll, &pcw, &postdiv, req->rate, 218 req->best_parent_rate); 219 220 req->rate = __mtk_pll_recalc_rate(pll, req->best_parent_rate, pcw, 221 postdiv); 222 223 return 0; 224 } 225 226 int mtk_pll_prepare(struct clk_hw *hw) 227 { 228 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 229 u32 r; 230 231 r = readl(pll->pwr_addr) | CON0_PWR_ON; 232 writel(r, pll->pwr_addr); 233 udelay(1); 234 235 r = readl(pll->pwr_addr) & ~CON0_ISO_EN; 236 writel(r, pll->pwr_addr); 237 udelay(1); 238 239 r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit); 240 writel(r, pll->en_addr); 241 242 if (pll->data->en_mask) { 243 r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask; 244 writel(r, pll->base_addr + REG_CON0); 245 } 246 247 __mtk_pll_tuner_enable(pll); 248 249 udelay(20); 250 251 if (pll->data->flags & HAVE_RST_BAR) { 252 r = readl(pll->base_addr + REG_CON0); 253 r |= pll->data->rst_bar_mask; 254 writel(r, pll->base_addr + REG_CON0); 255 } 256 257 return 0; 258 } 259 260 void mtk_pll_unprepare(struct clk_hw *hw) 261 { 262 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 263 u32 r; 264 265 if (pll->data->flags & HAVE_RST_BAR) { 266 r = readl(pll->base_addr + REG_CON0); 267 r &= ~pll->data->rst_bar_mask; 268 writel(r, pll->base_addr + REG_CON0); 269 } 270 271 __mtk_pll_tuner_disable(pll); 272 273 if (pll->data->en_mask) { 274 r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask; 275 writel(r, pll->base_addr + REG_CON0); 276 } 277 278 r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit); 279 writel(r, pll->en_addr); 280 281 r = readl(pll->pwr_addr) | CON0_ISO_EN; 282 writel(r, pll->pwr_addr); 283 284 r = readl(pll->pwr_addr) & ~CON0_PWR_ON; 285 writel(r, pll->pwr_addr); 286 } 287 288 static int mtk_pll_prepare_setclr(struct clk_hw *hw) 289 { 290 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 291 292 writel(BIT(pll->data->pll_en_bit), pll->en_set_addr); 293 294 /* Wait 20us after enable for the PLL to stabilize */ 295 udelay(20); 296 297 return 0; 298 } 299 300 static void mtk_pll_unprepare_setclr(struct clk_hw *hw) 301 { 302 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 303 304 writel(BIT(pll->data->pll_en_bit), pll->en_clr_addr); 305 } 306 307 const struct clk_ops mtk_pll_ops = { 308 .is_prepared = mtk_pll_is_prepared, 309 .prepare = mtk_pll_prepare, 310 .unprepare = mtk_pll_unprepare, 311 .recalc_rate = mtk_pll_recalc_rate, 312 .determine_rate = mtk_pll_determine_rate, 313 .set_rate = mtk_pll_set_rate, 314 }; 315 316 const struct clk_ops mtk_pll_fenc_clr_set_ops = { 317 .is_prepared = mtk_pll_fenc_is_prepared, 318 .prepare = mtk_pll_prepare_setclr, 319 .unprepare = mtk_pll_unprepare_setclr, 320 .recalc_rate = mtk_pll_recalc_rate, 321 .determine_rate = mtk_pll_determine_rate, 322 .set_rate = mtk_pll_set_rate, 323 }; 324 EXPORT_SYMBOL_GPL(mtk_pll_fenc_clr_set_ops); 325 326 struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, 327 const struct mtk_pll_data *data, 328 void __iomem *base, 329 const struct clk_ops *pll_ops) 330 { 331 struct clk_init_data init = {}; 332 int ret; 333 const char *parent_name = "clk26m"; 334 335 pll->base_addr = base + data->reg; 336 pll->pwr_addr = base + data->pwr_reg; 337 pll->pd_addr = base + data->pd_reg; 338 pll->pcw_addr = base + data->pcw_reg; 339 if (data->pcw_chg_reg) 340 pll->pcw_chg_addr = base + data->pcw_chg_reg; 341 else 342 pll->pcw_chg_addr = pll->base_addr + REG_CON1; 343 if (data->tuner_reg) 344 pll->tuner_addr = base + data->tuner_reg; 345 if (data->tuner_en_reg || data->tuner_en_bit) 346 pll->tuner_en_addr = base + data->tuner_en_reg; 347 if (data->en_reg) 348 pll->en_addr = base + data->en_reg; 349 else 350 pll->en_addr = pll->base_addr + REG_CON0; 351 if (data->en_set_reg) 352 pll->en_set_addr = base + data->en_set_reg; 353 if (data->en_clr_reg) 354 pll->en_clr_addr = base + data->en_clr_reg; 355 pll->hw.init = &init; 356 pll->data = data; 357 358 pll->fenc_addr = base + data->fenc_sta_ofs; 359 360 init.name = data->name; 361 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; 362 if (data->flags & PLL_PARENT_EN) 363 init.flags |= CLK_OPS_PARENT_ENABLE; 364 365 init.ops = pll_ops; 366 if (data->parent_name) 367 init.parent_names = &data->parent_name; 368 else 369 init.parent_names = &parent_name; 370 init.num_parents = 1; 371 372 ret = clk_hw_register(pll->dev, &pll->hw); 373 374 if (ret) 375 return ERR_PTR(ret); 376 377 return &pll->hw; 378 } 379 380 struct clk_hw *mtk_clk_register_pll(struct device *dev, 381 const struct mtk_pll_data *data, 382 void __iomem *base) 383 { 384 struct mtk_clk_pll *pll; 385 struct clk_hw *hw; 386 const struct clk_ops *pll_ops = data->ops ? data->ops : &mtk_pll_ops; 387 388 pll = kzalloc_obj(*pll); 389 if (!pll) 390 return ERR_PTR(-ENOMEM); 391 392 pll->dev = dev; 393 394 hw = mtk_clk_register_pll_ops(pll, data, base, pll_ops); 395 if (IS_ERR(hw)) 396 kfree(pll); 397 398 return hw; 399 } 400 401 void mtk_clk_unregister_pll(struct clk_hw *hw) 402 { 403 struct mtk_clk_pll *pll; 404 405 if (!hw) 406 return; 407 408 pll = to_mtk_clk_pll(hw); 409 410 clk_hw_unregister(hw); 411 kfree(pll); 412 } 413 414 int mtk_clk_register_plls(struct device *dev, 415 const struct mtk_pll_data *plls, int num_plls, 416 struct clk_hw_onecell_data *clk_data) 417 { 418 void __iomem *base; 419 int i; 420 struct clk_hw *hw; 421 422 base = of_iomap(dev->of_node, 0); 423 if (!base) { 424 pr_err("%s(): ioremap failed\n", __func__); 425 return -EINVAL; 426 } 427 428 for (i = 0; i < num_plls; i++) { 429 const struct mtk_pll_data *pll = &plls[i]; 430 431 if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) { 432 pr_warn("%pOF: Trying to register duplicate clock ID: %d\n", 433 dev->of_node, pll->id); 434 continue; 435 } 436 437 hw = mtk_clk_register_pll(dev, pll, base); 438 439 if (IS_ERR(hw)) { 440 pr_err("Failed to register clk %s: %pe\n", pll->name, 441 hw); 442 goto err; 443 } 444 445 clk_data->hws[pll->id] = hw; 446 } 447 448 return 0; 449 450 err: 451 while (--i >= 0) { 452 const struct mtk_pll_data *pll = &plls[i]; 453 454 mtk_clk_unregister_pll(clk_data->hws[pll->id]); 455 clk_data->hws[pll->id] = ERR_PTR(-ENOENT); 456 } 457 458 iounmap(base); 459 460 return PTR_ERR(hw); 461 } 462 EXPORT_SYMBOL_GPL(mtk_clk_register_plls); 463 464 __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw, 465 const struct mtk_pll_data *data) 466 { 467 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 468 469 return pll->base_addr - data->reg; 470 } 471 472 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, 473 struct clk_hw_onecell_data *clk_data) 474 { 475 __iomem void *base = NULL; 476 int i; 477 478 if (!clk_data) 479 return; 480 481 for (i = num_plls; i > 0; i--) { 482 const struct mtk_pll_data *pll = &plls[i - 1]; 483 484 if (IS_ERR_OR_NULL(clk_data->hws[pll->id])) 485 continue; 486 487 /* 488 * This is quite ugly but unfortunately the clks don't have 489 * any device tied to them, so there's no place to store the 490 * pointer to the I/O region base address. We have to fetch 491 * it from one of the registered clks. 492 */ 493 base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll); 494 495 mtk_clk_unregister_pll(clk_data->hws[pll->id]); 496 clk_data->hws[pll->id] = ERR_PTR(-ENOENT); 497 } 498 499 iounmap(base); 500 } 501 EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls); 502 503 MODULE_LICENSE("GPL"); 504