1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Copyright (C) 2023 Collabora Ltd. 5 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6 */ 7 8 #include <dt-bindings/clock/mediatek,mt8365-clk.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 16 #include "clk-gate.h" 17 #include "clk-mtk.h" 18 #include "clk-mux.h" 19 20 static DEFINE_SPINLOCK(mt8365_clk_lock); 21 22 static const struct mtk_fixed_clk top_fixed_clks[] = { 23 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), 24 FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000), 25 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 26 75000000), 27 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000), 28 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 29 52500000), 30 }; 31 32 static const struct mtk_fixed_factor top_divs[] = { 33 FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", "clk26m", 1, 2), 34 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 35 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 36 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 37 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 38 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32), 39 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 40 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6), 41 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 42 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 43 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 44 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 45 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 46 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 47 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 48 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 49 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ_en", 1, 2), 50 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 51 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 52 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 53 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 54 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 55 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 56 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 57 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll", 1, 96), 58 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 59 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 60 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 61 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 62 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 63 FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1), 64 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 65 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 66 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 67 FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", "lvdspll", 1, 16), 68 FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "usb20_en", 1, 13), 69 FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4), 70 FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8), 71 FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", "usb20_192m_ck", 72 1, 16), 73 FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", "usb20_192m_ck", 74 1, 32), 75 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 76 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 77 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), 78 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), 79 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 80 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 81 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), 82 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), 83 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 84 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 85 FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", "dsppll", 1, 1), 86 FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", "dsppll", 1, 2), 87 FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", "dsppll", 1, 4), 88 FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", "dsppll", 1, 8), 89 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 1), 90 FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52), 91 }; 92 93 static const char * const axi_parents[] = { 94 "clk26m", 95 "syspll_d7", 96 "syspll1_d4", 97 "syspll3_d2" 98 }; 99 100 static const char * const mem_parents[] = { 101 "clk26m", 102 "mmpll_ck", 103 "syspll_d3", 104 "syspll1_d2" 105 }; 106 107 static const char * const mm_parents[] = { 108 "clk26m", 109 "mmpll_ck", 110 "syspll1_d2", 111 "syspll_d5", 112 "syspll1_d4", 113 "univpll_d5", 114 "univpll1_d2", 115 "mmpll_d2" 116 }; 117 118 static const char * const scp_parents[] = { 119 "clk26m", 120 "syspll4_d2", 121 "univpll2_d2", 122 "syspll1_d2", 123 "univpll1_d2", 124 "syspll_d3", 125 "univpll_d3" 126 }; 127 128 static const char * const mfg_parents[] = { 129 "clk26m", 130 "mfgpll_ck", 131 "syspll_d3", 132 "univpll_d3" 133 }; 134 135 static const char * const atb_parents[] = { 136 "clk26m", 137 "syspll1_d4", 138 "syspll1_d2" 139 }; 140 141 static const char * const camtg_parents[] = { 142 "clk26m", 143 "usb20_192m_d8", 144 "univpll2_d8", 145 "usb20_192m_d4", 146 "univpll2_d32", 147 "usb20_192m_d16", 148 "usb20_192m_d32" 149 }; 150 151 static const char * const uart_parents[] = { 152 "clk26m", 153 "univpll2_d8" 154 }; 155 156 static const char * const spi_parents[] = { 157 "clk26m", 158 "univpll2_d2", 159 "univpll2_d4", 160 "univpll2_d8" 161 }; 162 163 static const char * const msdc50_0_hc_parents[] = { 164 "clk26m", 165 "syspll1_d2", 166 "univpll1_d4", 167 "syspll2_d2" 168 }; 169 170 static const char * const msdc50_0_parents[] = { 171 "clk26m", 172 "msdcpll_ck", 173 "univpll1_d2", 174 "syspll1_d2", 175 "univpll_d5", 176 "syspll2_d2", 177 "univpll1_d4", 178 "syspll4_d2" 179 }; 180 181 static const char * const msdc50_2_parents[] = { 182 "clk26m", 183 "msdcpll_ck", 184 "univpll_d3", 185 "univpll1_d2", 186 "syspll1_d2", 187 "univpll2_d2", 188 "syspll2_d2", 189 "univpll1_d4" 190 }; 191 192 static const char * const msdc30_1_parents[] = { 193 "clk26m", 194 "msdcpll_d2", 195 "univpll2_d2", 196 "syspll2_d2", 197 "univpll1_d4", 198 "syspll1_d4", 199 "syspll2_d4", 200 "univpll2_d8" 201 }; 202 203 static const char * const audio_parents[] = { 204 "clk26m", 205 "syspll3_d4", 206 "syspll4_d4", 207 "syspll1_d16" 208 }; 209 210 static const char * const aud_intbus_parents[] = { 211 "clk26m", 212 "syspll1_d4", 213 "syspll4_d2" 214 }; 215 216 static const char * const aud_1_parents[] = { 217 "clk26m", 218 "apll1_ck" 219 }; 220 221 static const char * const aud_2_parents[] = { 222 "clk26m", 223 "apll2_ck" 224 }; 225 226 static const char * const aud_engen1_parents[] = { 227 "clk26m", 228 "apll1_d2", 229 "apll1_d4", 230 "apll1_d8" 231 }; 232 233 static const char * const aud_engen2_parents[] = { 234 "clk26m", 235 "apll2_d2", 236 "apll2_d4", 237 "apll2_d8" 238 }; 239 240 static const char * const aud_spdif_parents[] = { 241 "clk26m", 242 "univpll_d2" 243 }; 244 245 static const char * const disp_pwm_parents[] = { 246 "clk26m", 247 "univpll2_d4" 248 }; 249 250 static const char * const dxcc_parents[] = { 251 "clk26m", 252 "syspll1_d2", 253 "syspll1_d4", 254 "syspll1_d8" 255 }; 256 257 static const char * const ssusb_sys_parents[] = { 258 "clk26m", 259 "univpll3_d4", 260 "univpll2_d4", 261 "univpll3_d2" 262 }; 263 264 static const char * const spm_parents[] = { 265 "clk26m", 266 "syspll1_d8" 267 }; 268 269 static const char * const i2c_parents[] = { 270 "clk26m", 271 "univpll3_d4", 272 "univpll3_d2", 273 "syspll1_d8", 274 "syspll2_d8" 275 }; 276 277 static const char * const pwm_parents[] = { 278 "clk26m", 279 "univpll3_d4", 280 "syspll1_d8" 281 }; 282 283 static const char * const senif_parents[] = { 284 "clk26m", 285 "univpll1_d4", 286 "univpll1_d2", 287 "univpll2_d2" 288 }; 289 290 static const char * const aes_fde_parents[] = { 291 "clk26m", 292 "msdcpll_ck", 293 "univpll_d3", 294 "univpll2_d2", 295 "univpll1_d2", 296 "syspll1_d2" 297 }; 298 299 static const char * const dpi0_parents[] = { 300 "clk26m", 301 "lvdspll_d2", 302 "lvdspll_d4", 303 "lvdspll_d8", 304 "lvdspll_d16" 305 }; 306 307 static const char * const dsp_parents[] = { 308 "clk26m", 309 "sys_26m_d2", 310 "dsppll_ck", 311 "dsppll_d2", 312 "dsppll_d4", 313 "dsppll_d8" 314 }; 315 316 static const char * const nfi2x_parents[] = { 317 "clk26m", 318 "syspll2_d2", 319 "syspll_d7", 320 "syspll_d3", 321 "syspll2_d4", 322 "msdcpll_d2", 323 "univpll1_d2", 324 "univpll_d5" 325 }; 326 327 static const char * const nfiecc_parents[] = { 328 "clk26m", 329 "syspll4_d2", 330 "univpll2_d4", 331 "syspll_d7", 332 "univpll1_d2", 333 "syspll1_d2", 334 "univpll2_d2", 335 "syspll_d5" 336 }; 337 338 static const char * const ecc_parents[] = { 339 "clk26m", 340 "univpll2_d2", 341 "univpll1_d2", 342 "univpll_d3", 343 "syspll_d2" 344 }; 345 346 static const char * const eth_parents[] = { 347 "clk26m", 348 "univpll2_d8", 349 "syspll4_d4", 350 "syspll1_d8", 351 "syspll4_d2" 352 }; 353 354 static const char * const gcpu_parents[] = { 355 "clk26m", 356 "univpll_d3", 357 "univpll2_d2", 358 "syspll_d3", 359 "syspll2_d2" 360 }; 361 362 static const char * const gcpu_cpm_parents[] = { 363 "clk26m", 364 "univpll2_d2", 365 "syspll2_d2" 366 }; 367 368 static const char * const apu_parents[] = { 369 "clk26m", 370 "univpll_d2", 371 "apupll_ck", 372 "mmpll_ck", 373 "syspll_d3", 374 "univpll1_d2", 375 "syspll1_d2", 376 "syspll1_d4" 377 }; 378 379 static const char * const mbist_diag_parents[] = { 380 "clk26m", 381 "syspll4_d4", 382 "univpll2_d8" 383 }; 384 385 static const char * const apll_i2s_parents[] = { 386 "aud_1_sel", 387 "aud_2_sel" 388 }; 389 390 static struct mtk_composite top_misc_muxes[] = { 391 /* CLK_CFG_11 */ 392 MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents, 393 0x0ec, 0, 2, 7), 394 /* Audio MUX */ 395 MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1), 396 MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1), 397 MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1), 398 MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1), 399 MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1), 400 MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1), 401 MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1), 402 }; 403 404 #define CLK_CFG_UPDATE 0x004 405 #define CLK_CFG_UPDATE1 0x008 406 407 static const struct mtk_mux top_muxes[] = { 408 /* CLK_CFG_0 */ 409 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 410 0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE, 411 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 412 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 413 0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1), 414 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044, 415 0x048, 16, 3, 23, CLK_CFG_UPDATE, 2), 416 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040, 417 0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3), 418 /* CLK_CFG_1 */ 419 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 420 0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4), 421 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050, 422 0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5), 423 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 424 0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6), 425 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents, 426 0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7), 427 /* CLK_CFG_2 */ 428 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 429 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8), 430 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 431 0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9), 432 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel", 433 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2, 434 23, CLK_CFG_UPDATE, 10, 0), 435 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel", 436 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2, 437 31, CLK_CFG_UPDATE, 11, 0), 438 /* CLK_CFG_3 */ 439 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 440 msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7, 441 CLK_CFG_UPDATE, 12, 0), 442 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel", 443 msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15, 444 CLK_CFG_UPDATE, 13, 0), 445 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 446 msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23, 447 CLK_CFG_UPDATE, 14, 0), 448 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 449 0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE, 450 15), 451 /* CLK_CFG_4 */ 452 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 453 aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7, 454 CLK_CFG_UPDATE, 16), 455 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 456 0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17), 457 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 458 0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE, 459 18), 460 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 461 aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31, 462 CLK_CFG_UPDATE, 19), 463 /* CLK_CFG_5 */ 464 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 465 aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7, 466 CLK_CFG_UPDATE, 20), 467 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SPDIF_SEL, "aud_spdif_sel", 468 aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15, 469 CLK_CFG_UPDATE, 21), 470 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 471 disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23, 472 CLK_CFG_UPDATE, 22), 473 /* CLK_CFG_6 */ 474 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents, 475 0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE, 476 24, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 477 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel", 478 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15, 479 CLK_CFG_UPDATE, 25), 480 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 481 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23, 482 CLK_CFG_UPDATE, 26), 483 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, 484 0x0a0, 0x0a4, 0x0a8, 24, 1, 31, CLK_CFG_UPDATE, 485 27, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 486 /* CLK_CFG_7 */ 487 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0, 488 0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28), 489 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0, 490 0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29), 491 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENIF_SEL, "senif_sel", senif_parents, 492 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE, 493 30), 494 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel", 495 aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 496 CLK_CFG_UPDATE, 31), 497 /* CLK_CFG_8 */ 498 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", senif_parents, 499 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0), 500 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0, 501 0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1), 502 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0, 503 0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2), 504 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0, 505 0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3), 506 /* CLK_CFG_9 */ 507 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 508 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4), 509 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 510 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5), 511 MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0, 512 0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6), 513 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0, 514 0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7), 515 /* CLK_CFG_10 */ 516 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0, 517 0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8), 518 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_CPM_SEL, "gcpu_cpm_sel", 519 gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, 520 CLK_CFG_UPDATE1, 9), 521 MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0, 522 0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10), 523 MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_IF_SEL, "apu_if_sel", apu_parents, 524 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1, 525 11), 526 }; 527 528 static const char * const mcu_bus_parents[] = { 529 "clk26m", 530 "armpll", 531 "mainpll", 532 "univpll_d2" 533 }; 534 535 static struct mtk_composite mcu_muxes[] = { 536 /* bus_pll_divider_cfg */ 537 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 538 9, 2, -1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 539 }; 540 541 #define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) { \ 542 .id = _id, \ 543 .name = _name, \ 544 .parent_name = _parent, \ 545 .div_reg = _reg, \ 546 .div_shift = _shift, \ 547 .div_width = _width, \ 548 .clk_divider_flags = _flags, \ 549 } 550 551 static const struct mtk_clk_divider top_adj_divs[] = { 552 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel", 553 0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 554 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel", 555 0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST), 556 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel", 557 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), 558 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel", 559 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), 560 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel", 561 0x328, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 562 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll_tdmout_sel", 563 0x328, 8, 8, CLK_DIVIDER_ROUND_CLOSEST), 564 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "apll_tdmin_sel", 565 0x328, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), 566 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll_tdmin_sel", 567 0x328, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), 568 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel", 569 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 570 }; 571 572 static const struct mtk_gate_regs top0_cg_regs = { 573 .set_ofs = 0, 574 .clr_ofs = 0, 575 .sta_ofs = 0, 576 }; 577 578 static const struct mtk_gate_regs top1_cg_regs = { 579 .set_ofs = 0x104, 580 .clr_ofs = 0x104, 581 .sta_ofs = 0x104, 582 }; 583 584 static const struct mtk_gate_regs top2_cg_regs = { 585 .set_ofs = 0x320, 586 .clr_ofs = 0x320, 587 .sta_ofs = 0x320, 588 }; 589 590 #define GATE_TOP0(_id, _name, _parent, _shift) \ 591 GATE_MTK(_id, _name, _parent, &top0_cg_regs, \ 592 _shift, &mtk_clk_gate_ops_no_setclr) 593 594 #define GATE_TOP1(_id, _name, _parent, _shift) \ 595 GATE_MTK(_id, _name, _parent, &top1_cg_regs, \ 596 _shift, &mtk_clk_gate_ops_no_setclr_inv) 597 598 #define GATE_TOP2(_id, _name, _parent, _shift) \ 599 GATE_MTK(_id, _name, _parent, &top2_cg_regs, \ 600 _shift, &mtk_clk_gate_ops_no_setclr_inv) 601 602 static const struct mtk_gate top_clk_gates[] = { 603 GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10), 604 GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m", 11), 605 GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16), 606 GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 17), 607 GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8), 608 GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 9), 609 GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 20), 610 GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21), 611 GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 22), 612 GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 23), 613 GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0), 614 GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1), 615 GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2), 616 GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3), 617 GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4), 618 GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5), 619 GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6), 620 GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7), 621 GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8), 622 }; 623 624 static const struct mtk_gate_regs ifr2_cg_regs = { 625 .set_ofs = 0x80, 626 .clr_ofs = 0x84, 627 .sta_ofs = 0x90, 628 }; 629 630 static const struct mtk_gate_regs ifr3_cg_regs = { 631 .set_ofs = 0x88, 632 .clr_ofs = 0x8c, 633 .sta_ofs = 0x94, 634 }; 635 636 static const struct mtk_gate_regs ifr4_cg_regs = { 637 .set_ofs = 0xa4, 638 .clr_ofs = 0xa8, 639 .sta_ofs = 0xac, 640 }; 641 642 static const struct mtk_gate_regs ifr5_cg_regs = { 643 .set_ofs = 0xc0, 644 .clr_ofs = 0xc4, 645 .sta_ofs = 0xc8, 646 }; 647 648 static const struct mtk_gate_regs ifr6_cg_regs = { 649 .set_ofs = 0xd0, 650 .clr_ofs = 0xd4, 651 .sta_ofs = 0xd8, 652 }; 653 654 #define GATE_IFRX(_id, _name, _parent, _shift, _regs) \ 655 GATE_MTK(_id, _name, _parent, _regs, _shift, \ 656 &mtk_clk_gate_ops_setclr) 657 658 #define GATE_IFR2(_id, _name, _parent, _shift) \ 659 GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs) 660 661 #define GATE_IFR3(_id, _name, _parent, _shift) \ 662 GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs) 663 664 #define GATE_IFR4(_id, _name, _parent, _shift) \ 665 GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs) 666 667 #define GATE_IFR5(_id, _name, _parent, _shift) \ 668 GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs) 669 670 #define GATE_IFR6(_id, _name, _parent, _shift) \ 671 GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs) 672 673 static const struct mtk_gate ifr_clks[] = { 674 /* IFR2 */ 675 GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0), 676 GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "clk26m", 1), 677 GATE_IFR2(CLK_IFR_PMIC_MD, "ifr_pmic_md", "clk26m", 2), 678 GATE_IFR2(CLK_IFR_PMIC_CONN, "ifr_pmic_conn", "clk26m", 3), 679 GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_sel", 8), 680 GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_sel", 9), 681 GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_sel", 10), 682 GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_sel", 15), 683 GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "pwm_sel", 16), 684 GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "pwm_sel", 17), 685 GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "pwm_sel", 18), 686 GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "pwm_sel", 19), 687 GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "pwm_sel", 20), 688 GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "pwm_sel", 21), 689 GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22), 690 GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23), 691 GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24), 692 GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26), 693 GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m", 27), 694 GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_cq_dma_fpc", "axi_sel", 28), 695 GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_sel", 31), 696 /* IFR3 */ 697 GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_sel", 1), 698 GATE_IFR3(CLK_IFR_MSDC0_HCLK, "ifr_msdc0", "msdc50_0_hc_sel", 2), 699 GATE_IFR3(CLK_IFR_MSDC2_HCLK, "ifr_msdc2", "msdc2_2_hc_sel", 3), 700 GATE_IFR3(CLK_IFR_MSDC1_HCLK, "ifr_msdc1", "axi_sel", 4), 701 GATE_IFR3(CLK_IFR_DVFSRC, "ifr_dvfsrc", "clk26m", 7), 702 GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8), 703 GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9), 704 GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10), 705 GATE_IFR3(CLK_IFR_CPUM, "ifr_cpum", "clk26m", 11), 706 GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14), 707 GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18), 708 GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24), 709 GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_sel", 25), 710 /* IFR4 */ 711 GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0), 712 GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "disp_pwm_sel", 2), 713 GATE_IFR4(CLK_IFR_AUD_26M_BK, "ifr_aud_26m_bk", "clk26m", 4), 714 GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_sel", 27), 715 /* IFR5 */ 716 GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0), 717 GATE_IFR5(CLK_IFR_MSDC1_SF, "ifr_msdc1_sf", "msdc50_0_sel", 1), 718 GATE_IFR5(CLK_IFR_MSDC2_SF, "ifr_msdc2_sf", "msdc50_0_sel", 2), 719 GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_sel", 7), 720 GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_sel", 8), 721 GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_src", "msdc50_0_sel", 9), 722 GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_src", "msdc30_1_sel", 10), 723 GATE_IFR5(CLK_IFR_MSDC2_SRC, "ifr_msdc2_src", "msdc50_2_sel", 11), 724 GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12), 725 GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13), 726 GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14), 727 GATE_MTK_FLAGS(CLK_IFR_MCU_PM_BK, "ifr_mcu_pm_bk", NULL, &ifr5_cg_regs, 728 17, &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED), 729 GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22), 730 GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23), 731 GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24), 732 GATE_IFR5(CLK_IFR_I2C1_AXI, "ifr_i2c1_axi", "i2c_sel", 25), 733 GATE_IFR5(CLK_IFR_I2C2_AXI, "ifr_i2c2_axi", "i2c_sel", 26), 734 GATE_IFR5(CLK_IFR_I2C3_AXI, "ifr_i2c3_axi", "i2c_sel", 27), 735 GATE_IFR5(CLK_IFR_NIC_AXI, "ifr_nic_axi", "axi_sel", 28), 736 GATE_IFR5(CLK_IFR_NIC_SLV_AXI, "ifr_nic_slv_axi", "axi_sel", 29), 737 GATE_IFR5(CLK_IFR_APU_AXI, "ifr_apu_axi", "axi_sel", 30), 738 /* IFR6 */ 739 GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0), 740 GATE_IFR6(CLK_IFR_NFI1X_BK, "ifr_nfi1x_bk", "nfi2x_sel", 1), 741 GATE_IFR6(CLK_IFR_NFIECC_BK, "ifr_nfiecc_bk", "nfi2x_sel", 2), 742 GATE_IFR6(CLK_IFR_NFI_BK, "ifr_nfi_bk", "axi_sel", 3), 743 GATE_IFR6(CLK_IFR_MSDC2_AP_BK, "ifr_msdc2_ap_bk", "axi_sel", 4), 744 GATE_IFR6(CLK_IFR_MSDC2_MD_BK, "ifr_msdc2_md_bk", "axi_sel", 5), 745 GATE_IFR6(CLK_IFR_MSDC2_BK, "ifr_msdc2_bk", "axi_sel", 6), 746 GATE_IFR6(CLK_IFR_SUSB_133_BK, "ifr_susb_133_bk", "axi_sel", 7), 747 GATE_IFR6(CLK_IFR_SUSB_66_BK, "ifr_susb_66_bk", "axi_sel", 8), 748 GATE_IFR6(CLK_IFR_SSUSB_SYS, "ifr_ssusb_sys", "ssusb_sys_sel", 9), 749 GATE_IFR6(CLK_IFR_SSUSB_REF, "ifr_ssusb_ref", "ssusb_sys_sel", 10), 750 GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11), 751 }; 752 753 static const struct mtk_gate_regs peri_cg_regs = { 754 .set_ofs = 0x20c, 755 .clr_ofs = 0x20c, 756 .sta_ofs = 0x20c, 757 }; 758 759 static const struct mtk_gate peri_clks[] = { 760 GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31, 761 &mtk_clk_gate_ops_no_setclr), 762 }; 763 764 static const struct mtk_clk_desc topck_desc = { 765 .clks = top_clk_gates, 766 .num_clks = ARRAY_SIZE(top_clk_gates), 767 .fixed_clks = top_fixed_clks, 768 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 769 .factor_clks = top_divs, 770 .num_factor_clks = ARRAY_SIZE(top_divs), 771 .mux_clks = top_muxes, 772 .num_mux_clks = ARRAY_SIZE(top_muxes), 773 .composite_clks = top_misc_muxes, 774 .num_composite_clks = ARRAY_SIZE(top_misc_muxes), 775 .divider_clks = top_adj_divs, 776 .num_divider_clks = ARRAY_SIZE(top_adj_divs), 777 .clk_lock = &mt8365_clk_lock, 778 }; 779 780 static const struct mtk_clk_desc infra_desc = { 781 .clks = ifr_clks, 782 .num_clks = ARRAY_SIZE(ifr_clks), 783 }; 784 785 static const struct mtk_clk_desc peri_desc = { 786 .clks = peri_clks, 787 .num_clks = ARRAY_SIZE(peri_clks), 788 }; 789 790 static const struct mtk_clk_desc mcu_desc = { 791 .composite_clks = mcu_muxes, 792 .num_composite_clks = ARRAY_SIZE(mcu_muxes), 793 .clk_lock = &mt8365_clk_lock, 794 }; 795 796 static const struct of_device_id of_match_clk_mt8365[] = { 797 { .compatible = "mediatek,mt8365-topckgen", .data = &topck_desc }, 798 { .compatible = "mediatek,mt8365-infracfg", .data = &infra_desc }, 799 { .compatible = "mediatek,mt8365-pericfg", .data = &peri_desc }, 800 { .compatible = "mediatek,mt8365-mcucfg", .data = &mcu_desc }, 801 { /* sentinel */ } 802 }; 803 MODULE_DEVICE_TABLE(of, of_match_clk_mt8365); 804 805 static struct platform_driver clk_mt8365_drv = { 806 .driver = { 807 .name = "clk-mt8365", 808 .of_match_table = of_match_clk_mt8365, 809 }, 810 .probe = mtk_clk_simple_probe, 811 .remove = mtk_clk_simple_remove, 812 }; 813 module_platform_driver(clk_mt8365_drv); 814 815 MODULE_DESCRIPTION("MediaTek MT8365 main clocks driver"); 816 MODULE_LICENSE("GPL"); 817