1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Copyright (c) 2022 BayLibre, SAS 5 */ 6 7 #include <dt-bindings/clock/mediatek,mt8365-clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/platform_device.h> 10 11 #include "clk-gate.h" 12 #include "clk-mtk.h" 13 14 static const struct mtk_gate_regs mm0_cg_regs = { 15 .set_ofs = 0x104, 16 .clr_ofs = 0x108, 17 .sta_ofs = 0x100, 18 }; 19 20 static const struct mtk_gate_regs mm1_cg_regs = { 21 .set_ofs = 0x114, 22 .clr_ofs = 0x118, 23 .sta_ofs = 0x110, 24 }; 25 26 #define GATE_MM0(_id, _name, _parent, _shift) \ 27 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \ 28 &mtk_clk_gate_ops_setclr) 29 30 #define GATE_MM1(_id, _name, _parent, _shift) \ 31 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \ 32 &mtk_clk_gate_ops_setclr) 33 34 static const struct mtk_gate mm_clks[] = { 35 /* MM0 */ 36 GATE_MM0(CLK_MM_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 0), 37 GATE_MM0(CLK_MM_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_sel", 1), 38 GATE_MM0(CLK_MM_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 2), 39 GATE_MM0(CLK_MM_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 3), 40 GATE_MM0(CLK_MM_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 4), 41 GATE_MM0(CLK_MM_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 5), 42 GATE_MM0(CLK_MM_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 6), 43 GATE_MM0(CLK_MM_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 7), 44 GATE_MM0(CLK_MM_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 8), 45 GATE_MM0(CLK_MM_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_sel", 9), 46 GATE_MM0(CLK_MM_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 10), 47 GATE_MM0(CLK_MM_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 11), 48 GATE_MM0(CLK_MM_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 12), 49 GATE_MM0(CLK_MM_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 13), 50 GATE_MM0(CLK_MM_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 14), 51 GATE_MM0(CLK_MM_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 15), 52 GATE_MM0(CLK_MM_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 16), 53 GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17), 54 GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18), 55 GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19), 56 GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20), 57 GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21), 58 GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22), 59 GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23), 60 GATE_MM0(CLK_MM_MM_SMI_COMM0, "mm_smi_comm0", "mm_sel", 24), 61 GATE_MM0(CLK_MM_MM_SMI_COMM1, "mm_smi_comm1", "mm_sel", 25), 62 GATE_MM0(CLK_MM_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 26), 63 GATE_MM0(CLK_MM_MM_SMI_IMG, "mm_smi_img", "mm_sel", 27), 64 GATE_MM0(CLK_MM_MM_SMI_CAM, "mm_smi_cam", "mm_sel", 28), 65 GATE_MM0(CLK_MM_IMG_IMG_DL_RELAY, "mm_dl_relay", "mm_sel", 29), 66 GATE_MM0(CLK_MM_IMG_IMG_DL_ASYNC_TOP, "mm_dl_async_top", "mm_sel", 30), 67 GATE_MM0(CLK_MM_DSI0_DIG_DSI, "mm_dsi0_dig_dsi", "dsi0_lntc_dsick", 31), 68 /* MM1 */ 69 GATE_MM1(CLK_MM_26M_HRTWT, "mm_f26m_hrtwt", "clk26m", 0), 70 GATE_MM1(CLK_MM_MM_DPI0, "mm_dpi0", "mm_sel", 1), 71 GATE_MM1(CLK_MM_LVDSTX_PXL, "mm_flvdstx_pxl", "vpll_dpix", 2), 72 GATE_MM1(CLK_MM_LVDSTX_CTS, "mm_flvdstx_cts", "lvdstx_dig_cts", 3), 73 }; 74 75 static const struct mtk_clk_desc mm_desc = { 76 .clks = mm_clks, 77 .num_clks = ARRAY_SIZE(mm_clks), 78 }; 79 80 static const struct platform_device_id clk_mt8365_mm_id_table[] = { 81 { .name = "clk-mt8365-mm", .driver_data = (kernel_ulong_t)&mm_desc }, 82 { /* sentinel */ } 83 }; 84 MODULE_DEVICE_TABLE(platform, clk_mt8365_mm_id_table); 85 86 static struct platform_driver clk_mt8365_mm_drv = { 87 .probe = mtk_clk_pdev_probe, 88 .remove = mtk_clk_pdev_remove, 89 .driver = { 90 .name = "clk-mt8365-mm", 91 }, 92 .id_table = clk_mt8365_mm_id_table, 93 }; 94 module_platform_driver(clk_mt8365_mm_drv); 95 96 MODULE_DESCRIPTION("MediaTek MT8365 MultiMedia clocks driver"); 97 MODULE_LICENSE("GPL"); 98