xref: /linux/drivers/clk/mediatek/clk-mt8365-cam.c (revision 87807f77a03d0271211b75f84b2a8b88f4e8e5d4)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2022 MediaTek Inc.
4  */
5 
6 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
9 
10 #include "clk-gate.h"
11 #include "clk-mtk.h"
12 
13 static const struct mtk_gate_regs cam_cg_regs = {
14 	.set_ofs = 0x4,
15 	.clr_ofs = 0x8,
16 	.sta_ofs = 0x0,
17 };
18 
19 #define GATE_CAM(_id, _name, _parent, _shift) \
20 		GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
21 			 &mtk_clk_gate_ops_setclr)
22 
23 static const struct mtk_gate cam_clks[] = {
24 	GATE_CAM(CLK_CAM_LARB2, "cam_larb2", "mm_sel", 0),
25 	GATE_CAM(CLK_CAM, "cam", "mm_sel", 6),
26 	GATE_CAM(CLK_CAMTG, "camtg", "mm_sel", 7),
27 	GATE_CAM(CLK_CAM_SENIF, "cam_senif", "mm_sel", 8),
28 	GATE_CAM(CLK_CAMSV0, "camsv0", "mm_sel", 9),
29 	GATE_CAM(CLK_CAMSV1, "camsv1", "mm_sel", 10),
30 	GATE_CAM(CLK_CAM_FDVT, "cam_fdvt", "mm_sel", 11),
31 	GATE_CAM(CLK_CAM_WPE, "cam_wpe", "mm_sel", 12),
32 };
33 
34 static const struct mtk_clk_desc cam_desc = {
35 	.clks = cam_clks,
36 	.num_clks = ARRAY_SIZE(cam_clks),
37 };
38 
39 static const struct of_device_id of_match_clk_mt8365_cam[] = {
40 	{
41 		.compatible = "mediatek,mt8365-imgsys",
42 		.data = &cam_desc,
43 	}, {
44 		/* sentinel */
45 	}
46 };
47 MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_cam);
48 
49 static struct platform_driver clk_mt8365_cam_drv = {
50 	.probe = mtk_clk_simple_probe,
51 	.remove = mtk_clk_simple_remove,
52 	.driver = {
53 		.name = "clk-mt8365-cam",
54 		.of_match_table = of_match_clk_mt8365_cam,
55 	},
56 };
57 module_platform_driver(clk_mt8365_cam_drv);
58 MODULE_LICENSE("GPL");
59