1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025 MediaTek Inc. 4 * Guangjie Song <guangjie.song@mediatek.com> 5 * Copyright (c) 2025 Collabora Ltd. 6 * Laura Nao <laura.nao@collabora.com> 7 */ 8 #include <dt-bindings/clock/mediatek,mt8196-clock.h> 9 10 #include <linux/clk.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 17 #include "clk-mtk.h" 18 #include "clk-pll.h" 19 20 #define MFGPLL_CON0 0x008 21 #define MFGPLL_CON1 0x00c 22 #define MFGPLL_CON2 0x010 23 #define MFGPLL_CON3 0x014 24 #define MFGPLL_SC0_CON0 0x008 25 #define MFGPLL_SC0_CON1 0x00c 26 #define MFGPLL_SC0_CON2 0x010 27 #define MFGPLL_SC0_CON3 0x014 28 #define MFGPLL_SC1_CON0 0x008 29 #define MFGPLL_SC1_CON1 0x00c 30 #define MFGPLL_SC1_CON2 0x010 31 #define MFGPLL_SC1_CON3 0x014 32 33 #define MT8196_PLL_FMAX (3800UL * MHZ) 34 #define MT8196_PLL_FMIN (1500UL * MHZ) 35 #define MT8196_INTEGER_BITS 8 36 37 #define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \ 38 _flags, _rst_bar_mask, \ 39 _pd_reg, _pd_shift, _tuner_reg, \ 40 _tuner_en_reg, _tuner_en_bit, \ 41 _pcw_reg, _pcw_shift, _pcwbits) { \ 42 .id = _id, \ 43 .name = _name, \ 44 .reg = _reg, \ 45 .en_reg = _en_reg, \ 46 .en_mask = _en_mask, \ 47 .pll_en_bit = _pll_en_bit, \ 48 .flags = _flags, \ 49 .rst_bar_mask = _rst_bar_mask, \ 50 .fmax = MT8196_PLL_FMAX, \ 51 .fmin = MT8196_PLL_FMIN, \ 52 .pd_reg = _pd_reg, \ 53 .pd_shift = _pd_shift, \ 54 .tuner_reg = _tuner_reg, \ 55 .tuner_en_reg = _tuner_en_reg, \ 56 .tuner_en_bit = _tuner_en_bit, \ 57 .pcw_reg = _pcw_reg, \ 58 .pcw_shift = _pcw_shift, \ 59 .pcwbits = _pcwbits, \ 60 .pcwibits = MT8196_INTEGER_BITS, \ 61 } 62 63 static const struct mtk_pll_data mfg_ao_plls[] = { 64 PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0, 65 BIT(0), MFGPLL_CON1, 24, 0, 0, 0, 66 MFGPLL_CON1, 0, 22), 67 }; 68 69 static const struct mtk_pll_data mfgsc0_ao_plls[] = { 70 PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0, 71 MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0, 72 MFGPLL_SC0_CON1, 0, 22), 73 }; 74 75 static const struct mtk_pll_data mfgsc1_ao_plls[] = { 76 PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0, 77 MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0, 78 MFGPLL_SC1_CON1, 0, 22), 79 }; 80 81 static const struct of_device_id of_match_clk_mt8196_mfg[] = { 82 { .compatible = "mediatek,mt8196-mfgpll-pll-ctrl", 83 .data = &mfg_ao_plls }, 84 { .compatible = "mediatek,mt8196-mfgpll-sc0-pll-ctrl", 85 .data = &mfgsc0_ao_plls }, 86 { .compatible = "mediatek,mt8196-mfgpll-sc1-pll-ctrl", 87 .data = &mfgsc1_ao_plls }, 88 { /* sentinel */ } 89 }; 90 MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mfg); 91 92 static int clk_mt8196_mfg_probe(struct platform_device *pdev) 93 { 94 const struct mtk_pll_data *plls; 95 struct clk_hw_onecell_data *clk_data; 96 struct device_node *node = pdev->dev.of_node; 97 const int num_plls = 1; 98 int r; 99 100 plls = of_device_get_match_data(&pdev->dev); 101 if (!plls) 102 return -EINVAL; 103 104 clk_data = mtk_alloc_clk_data(num_plls); 105 if (!clk_data) 106 return -ENOMEM; 107 108 r = mtk_clk_register_plls(node, plls, num_plls, clk_data); 109 if (r) 110 goto free_clk_data; 111 112 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 113 if (r) 114 goto unregister_plls; 115 116 platform_set_drvdata(pdev, clk_data); 117 118 return r; 119 120 unregister_plls: 121 mtk_clk_unregister_plls(plls, num_plls, clk_data); 122 free_clk_data: 123 mtk_free_clk_data(clk_data); 124 125 return r; 126 } 127 128 static void clk_mt8196_mfg_remove(struct platform_device *pdev) 129 { 130 const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev); 131 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); 132 struct device_node *node = pdev->dev.of_node; 133 134 of_clk_del_provider(node); 135 mtk_clk_unregister_plls(plls, 1, clk_data); 136 mtk_free_clk_data(clk_data); 137 } 138 139 static struct platform_driver clk_mt8196_mfg_drv = { 140 .probe = clk_mt8196_mfg_probe, 141 .remove = clk_mt8196_mfg_remove, 142 .driver = { 143 .name = "clk-mt8196-mfg", 144 .of_match_table = of_match_clk_mt8196_mfg, 145 }, 146 }; 147 module_platform_driver(clk_mt8196_mfg_drv); 148 149 MODULE_DESCRIPTION("MediaTek MT8196 GPU mfg clocks driver"); 150 MODULE_LICENSE("GPL"); 151