1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include "clk-gate.h" 7 #include "clk-mtk.h" 8 9 #include <dt-bindings/clock/mt8195-clk.h> 10 #include <dt-bindings/reset/mt8195-resets.h> 11 #include <linux/clk-provider.h> 12 #include <linux/platform_device.h> 13 14 static const struct mtk_gate_regs infra_ao0_cg_regs = { 15 .set_ofs = 0x80, 16 .clr_ofs = 0x84, 17 .sta_ofs = 0x90, 18 }; 19 20 static const struct mtk_gate_regs infra_ao1_cg_regs = { 21 .set_ofs = 0x88, 22 .clr_ofs = 0x8c, 23 .sta_ofs = 0x94, 24 }; 25 26 static const struct mtk_gate_regs infra_ao2_cg_regs = { 27 .set_ofs = 0xa4, 28 .clr_ofs = 0xa8, 29 .sta_ofs = 0xac, 30 }; 31 32 static const struct mtk_gate_regs infra_ao3_cg_regs = { 33 .set_ofs = 0xc0, 34 .clr_ofs = 0xc4, 35 .sta_ofs = 0xc8, 36 }; 37 38 static const struct mtk_gate_regs infra_ao4_cg_regs = { 39 .set_ofs = 0xe0, 40 .clr_ofs = 0xe4, 41 .sta_ofs = 0xe8, 42 }; 43 44 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ 45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \ 46 &mtk_clk_gate_ops_setclr, _flag) 47 48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ 49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0) 50 51 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ 52 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \ 53 &mtk_clk_gate_ops_setclr, _flag) 54 55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ 56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0) 57 58 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ 59 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \ 60 &mtk_clk_gate_ops_setclr, _flag) 61 62 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ 63 GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0) 64 65 #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \ 66 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \ 67 &mtk_clk_gate_ops_setclr, _flag) 68 69 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ 70 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0) 71 72 #define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \ 73 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \ 74 &mtk_clk_gate_ops_setclr, _flag) 75 76 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ 77 GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0) 78 79 static const struct mtk_gate infra_ao_clks[] = { 80 /* INFRA_AO0 */ 81 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0), 82 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1), 83 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2), 84 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3), 85 /* infra_ao_sej is main clock is for secure engine with JTAG support */ 86 GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL), 87 GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6), 88 GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8), 89 GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9), 90 GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10), 91 GATE_INFRA_AO0(CLK_INFRA_AO_PWM_H, "infra_ao_pwm_h", "top_axi", 15), 92 GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16), 93 GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17), 94 GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18), 95 GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19), 96 GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21), 97 GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22), 98 GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23), 99 GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24), 100 GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25), 101 GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26), 102 GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27), 103 GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_cq_dma_fpc", "fpc", 28), 104 GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29), 105 /* INFRA_AO1 */ 106 GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0), 107 GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1), 108 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc50_0_hclk", 2), 109 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4), 110 GATE_INFRA_AO1(CLK_INFRA_AO_CG1_MSDC2, "infra_ao_cg1_msdc2", "top_axi", 5), 111 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_src", "top_msdc50_0", 6), 112 GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9), 113 GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10), 114 GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11), 115 GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12), 116 GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_H, "infra_ao_cec_66m_h", "top_axi", 13), 117 GATE_INFRA_AO1(CLK_INFRA_AO_IRRX, "infra_ao_irrx", "top_axi", 14), 118 GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15), 119 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_src", "top_msdc30_1", 16), 120 GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_B, "infra_ao_cec_66m_b", "top_axi", 17), 121 GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18), 122 /* infra_ao_device_apc is for device access permission control module */ 123 GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_device_apc", "top_axi", 20, 124 CLK_IS_CRITICAL), 125 GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_H, "infra_ao_ecc_66m_h", "top_axi", 23), 126 GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24), 127 GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25), 128 GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26), 129 GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29), 130 GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc_f26m", "clk26m", 31), 131 /* INFRA_AO2 */ 132 GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0), 133 GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB, "infra_ao_ssusb", "top_usb_top", 1), 134 GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2), 135 GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_B, "infra_ao_cldma_b", "top_axi", 3), 136 GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_B, "infra_ao_audio_26m_b", "clk26m", 4), 137 GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6), 138 GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9), 139 GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10), 140 GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, "infra_ao_unipro_sys", "top_ufs", 11), 141 GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, "infra_ao_unipro_tick", "top_ufs_tick1us", 12), 142 GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, "infra_ao_ufs_mp_sap_b", "top_ufs_mp_sap_cfg", 13), 143 /* pwrmcu is used by ATF for platform PM: clocks must never be disabled by the kernel */ 144 GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "top_pwrmcu", 15, 145 CLK_IS_CRITICAL), 146 GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "top_axi", 17, 147 CLK_IS_CRITICAL), 148 GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, "infra_ao_apdma_b", "top_axi", 18), 149 GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25), 150 GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26), 151 GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27), 152 GATE_INFRA_AO2(CLK_INFRA_AO_AES_UFSFDE, "infra_ao_aes_ufsfde", "top_ufs", 28), 153 GATE_INFRA_AO2(CLK_INFRA_AO_AES, "infra_ao_aes", "top_aes_ufsfde", 29), 154 GATE_INFRA_AO2(CLK_INFRA_AO_UFS_TICK, "infra_ao_ufs_tick", "top_ufs_tick1us", 30), 155 GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_XHCI, "infra_ao_ssusb_xhci", "top_ssusb_xhci", 31), 156 /* INFRA_AO3 */ 157 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0f", "top_msdc50_0", 0), 158 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1f", "top_msdc50_0", 1), 159 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2f", "top_msdc50_0", 2), 160 GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5), 161 GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7), 162 GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8), 163 GATE_INFRA_AO3(CLK_INFRA_AO_CG3_MSDC2, "infra_ao_cg3_msdc2", "top_msdc30_2", 9), 164 GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10), 165 GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15), 166 GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_B, "infra_ao_gcpu_66m_b", "top_axi", 16), 167 GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_B, "infra_ao_gcpu_133m_b", "top_axi", 17), 168 GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20), 169 GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24), 170 /* infra_ao_device_apc_sync is for device access permission control module */ 171 GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_device_apc_sync", "top_axi", 25, 172 CLK_IS_CRITICAL), 173 GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26), 174 GATE_INFRA_AO3(CLK_INFRA_AO_SPIS0, "infra_ao_spis0", "top_spis", 28), 175 GATE_INFRA_AO3(CLK_INFRA_AO_SPIS1, "infra_ao_spis1", "top_spis", 29), 176 /* INFRA_AO4 */ 177 /* infra_ao_133m_m_peri infra_ao_66m_m_peri are main clocks of peripheral */ 178 GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_M_PERI, "infra_ao_133m_m_peri", "top_axi", 0, 179 CLK_IS_CRITICAL), 180 GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_M_PERI, "infra_ao_66m_m_peri", "top_axi", 1, 181 CLK_IS_CRITICAL), 182 GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", "pextp_pipe", 7), 183 GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P1, "infra_ao_pcie_pl_p_250m_p1", 184 "ssusb_u3phy_p1_p_p0", 8), 185 GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_P1_TL_96M, "infra_ao_pcie_p1_tl_96m", "top_tl_p1", 17), 186 GATE_INFRA_AO4(CLK_INFRA_AO_AES_MSDCFDE_0P, "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), 187 GATE_INFRA_AO4(CLK_INFRA_AO_UFS_TX_SYMBOL, "infra_ao_ufs_tx_symbol", "ufs_tx_symbol", 22), 188 GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL, "infra_ao_ufs_rx_symbol", "ufs_rx_symbol", 23), 189 GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL1, "infra_ao_ufs_rx_symbol1", "ufs_rx_symbol1", 24), 190 GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31), 191 }; 192 193 static u16 infra_ao_rst_ofs[] = { 194 INFRA_RST0_SET_OFFSET, 195 INFRA_RST1_SET_OFFSET, 196 INFRA_RST2_SET_OFFSET, 197 INFRA_RST3_SET_OFFSET, 198 INFRA_RST4_SET_OFFSET, 199 }; 200 201 static u16 infra_ao_idx_map[] = { 202 [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, 203 [MT8195_INFRA_RST2_USBSIF_P1_SWRST] = 2 * RST_NR_PER_BANK + 18, 204 [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26, 205 [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27, 206 [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, 207 [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10, 208 }; 209 210 static struct mtk_clk_rst_desc infra_ao_rst_desc = { 211 .version = MTK_RST_SET_CLR, 212 .rst_bank_ofs = infra_ao_rst_ofs, 213 .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), 214 .rst_idx_map = infra_ao_idx_map, 215 .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), 216 }; 217 218 static const struct mtk_clk_desc infra_ao_desc = { 219 .clks = infra_ao_clks, 220 .num_clks = ARRAY_SIZE(infra_ao_clks), 221 .rst_desc = &infra_ao_rst_desc, 222 }; 223 224 static const struct of_device_id of_match_clk_mt8195_infra_ao[] = { 225 { 226 .compatible = "mediatek,mt8195-infracfg_ao", 227 .data = &infra_ao_desc, 228 }, { 229 /* sentinel */ 230 } 231 }; 232 MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_infra_ao); 233 234 static struct platform_driver clk_mt8195_infra_ao_drv = { 235 .probe = mtk_clk_simple_probe, 236 .remove_new = mtk_clk_simple_remove, 237 .driver = { 238 .name = "clk-mt8195-infra_ao", 239 .of_match_table = of_match_clk_mt8195_infra_ao, 240 }, 241 }; 242 module_platform_driver(clk_mt8195_infra_ao_drv); 243 244 MODULE_DESCRIPTION("MediaTek MT8195 infracfg clocks driver"); 245 MODULE_LICENSE("GPL"); 246