1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/platform_device.h> 10 #include <linux/slab.h> 11 12 #include "clk-gate.h" 13 #include "clk-mtk.h" 14 #include "clk-mux.h" 15 16 #include <dt-bindings/clock/mt8192-clk.h> 17 #include <dt-bindings/reset/mt8192-resets.h> 18 19 static DEFINE_SPINLOCK(mt8192_clk_lock); 20 21 static const struct mtk_fixed_clk top_fixed_clks[] = { 22 FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000), 23 }; 24 25 static const struct mtk_fixed_factor top_divs[] = { 26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0), 27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0), 28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0), 29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0), 30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0), 31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0), 32 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0), 33 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0), 34 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0), 35 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0), 36 FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0), 37 FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0), 38 FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0), 39 FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0), 40 FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0), 41 FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0), 42 FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0), 43 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0), 44 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0), 45 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0), 46 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0), 47 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0), 48 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0), 49 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0), 50 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0), 51 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0), 52 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0), 53 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0), 54 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0), 55 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0), 56 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0), 57 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0), 58 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 59 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 60 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 61 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 62 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 63 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 64 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 65 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 66 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 67 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 68 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 69 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 70 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 71 FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2), 72 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 73 FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9), 74 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2), 75 FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1), 76 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 77 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), 78 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 79 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 80 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 81 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 82 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 83 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 84 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2), 85 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4), 86 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8), 87 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), 88 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16), 89 FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), 90 FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), 91 FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1), 92 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0), 93 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0), 94 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0), 95 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0), 96 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0), 97 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0), 98 }; 99 100 static const char * const axi_parents[] = { 101 "clk26m", 102 "mainpll_d4_d4", 103 "mainpll_d7_d2", 104 "mainpll_d4_d2", 105 "mainpll_d5_d2", 106 "mainpll_d6_d2", 107 "osc_d4" 108 }; 109 110 static const char * const spm_parents[] = { 111 "clk26m", 112 "osc_d10", 113 "mainpll_d7_d4", 114 "clk32k" 115 }; 116 117 static const char * const scp_parents[] = { 118 "clk26m", 119 "univpll_d5", 120 "mainpll_d6_d2", 121 "mainpll_d6", 122 "univpll_d6", 123 "mainpll_d4_d2", 124 "mainpll_d5_d2", 125 "univpll_d4_d2" 126 }; 127 128 static const char * const bus_aximem_parents[] = { 129 "clk26m", 130 "mainpll_d7_d2", 131 "mainpll_d4_d2", 132 "mainpll_d5_d2", 133 "mainpll_d6" 134 }; 135 136 static const char * const disp_parents[] = { 137 "clk26m", 138 "univpll_d6_d2", 139 "mainpll_d5_d2", 140 "mmpll_d6_d2", 141 "univpll_d5_d2", 142 "univpll_d4_d2", 143 "mmpll_d7", 144 "univpll_d6", 145 "mainpll_d4", 146 "mmpll_d5_d2" 147 }; 148 149 static const char * const mdp_parents[] = { 150 "clk26m", 151 "mainpll_d5_d2", 152 "mmpll_d6_d2", 153 "mainpll_d4_d2", 154 "mmpll_d4_d2", 155 "mainpll_d6", 156 "univpll_d6", 157 "mainpll_d4", 158 "tvdpll_ck", 159 "univpll_d4", 160 "mmpll_d5_d2" 161 }; 162 163 static const char * const img_parents[] = { 164 "clk26m", 165 "univpll_d4", 166 "tvdpll_ck", 167 "mainpll_d4", 168 "univpll_d5", 169 "mmpll_d6", 170 "univpll_d6", 171 "mainpll_d6", 172 "mmpll_d4_d2", 173 "mainpll_d4_d2", 174 "mmpll_d6_d2", 175 "mmpll_d5_d2" 176 }; 177 178 static const char * const ipe_parents[] = { 179 "clk26m", 180 "mainpll_d4", 181 "mmpll_d6", 182 "univpll_d6", 183 "mainpll_d6", 184 "univpll_d4_d2", 185 "mainpll_d4_d2", 186 "mmpll_d6_d2", 187 "mmpll_d5_d2" 188 }; 189 190 static const char * const dpe_parents[] = { 191 "clk26m", 192 "mainpll_d4", 193 "mmpll_d6", 194 "univpll_d6", 195 "mainpll_d6", 196 "univpll_d4_d2", 197 "univpll_d5_d2", 198 "mmpll_d6_d2" 199 }; 200 201 static const char * const cam_parents[] = { 202 "clk26m", 203 "mainpll_d4", 204 "mmpll_d6", 205 "univpll_d4", 206 "univpll_d5", 207 "univpll_d6", 208 "mmpll_d7", 209 "univpll_d4_d2", 210 "mainpll_d4_d2", 211 "univpll_d6_d2" 212 }; 213 214 static const char * const ccu_parents[] = { 215 "clk26m", 216 "mainpll_d4", 217 "mmpll_d6", 218 "mainpll_d6", 219 "mmpll_d7", 220 "univpll_d4_d2", 221 "mmpll_d6_d2", 222 "mmpll_d5_d2", 223 "univpll_d5", 224 "univpll_d6_d2" 225 }; 226 227 static const char * const dsp7_parents[] = { 228 "clk26m", 229 "mainpll_d4_d2", 230 "mainpll_d6", 231 "mmpll_d6", 232 "univpll_d5", 233 "mmpll_d5", 234 "univpll_d4", 235 "mmpll_d4" 236 }; 237 238 static const char * const mfg_ref_parents[] = { 239 "clk26m", 240 "clk26m", 241 "univpll_d6", 242 "mainpll_d5_d2" 243 }; 244 245 static const char * const mfg_pll_parents[] = { 246 "mfg_ref_sel", 247 "mfgpll" 248 }; 249 250 static const char * const camtg_parents[] = { 251 "clk26m", 252 "univpll_192m_d8", 253 "univpll_d6_d8", 254 "univpll_192m_d4", 255 "univpll_d6_d16", 256 "csw_f26m_d2", 257 "univpll_192m_d16", 258 "univpll_192m_d32" 259 }; 260 261 static const char * const uart_parents[] = { 262 "clk26m", 263 "univpll_d6_d8" 264 }; 265 266 static const char * const spi_parents[] = { 267 "clk26m", 268 "mainpll_d5_d4", 269 "mainpll_d6_d4", 270 "msdcpll_d4" 271 }; 272 273 static const char * const msdc50_0_h_parents[] = { 274 "clk26m", 275 "mainpll_d4_d2", 276 "mainpll_d6_d2" 277 }; 278 279 static const char * const msdc50_0_parents[] = { 280 "clk26m", 281 "msdcpll_ck", 282 "msdcpll_d2", 283 "univpll_d4_d4", 284 "mainpll_d6_d2", 285 "univpll_d4_d2" 286 }; 287 288 static const char * const msdc30_parents[] = { 289 "clk26m", 290 "univpll_d6_d2", 291 "mainpll_d6_d2", 292 "mainpll_d7_d2", 293 "msdcpll_d2" 294 }; 295 296 static const char * const audio_parents[] = { 297 "clk26m", 298 "mainpll_d5_d8", 299 "mainpll_d7_d8", 300 "mainpll_d4_d16" 301 }; 302 303 static const char * const aud_intbus_parents[] = { 304 "clk26m", 305 "mainpll_d4_d4", 306 "mainpll_d7_d4" 307 }; 308 309 static const char * const pwrap_ulposc_parents[] = { 310 "osc_d10", 311 "clk26m", 312 "osc_d4", 313 "osc_d8", 314 "osc_d16" 315 }; 316 317 static const char * const atb_parents[] = { 318 "clk26m", 319 "mainpll_d4_d2", 320 "mainpll_d5_d2" 321 }; 322 323 static const char * const dpi_parents[] = { 324 "clk26m", 325 "tvdpll_d2", 326 "tvdpll_d4", 327 "tvdpll_d8", 328 "tvdpll_d16" 329 }; 330 331 static const char * const scam_parents[] = { 332 "clk26m", 333 "mainpll_d5_d4" 334 }; 335 336 static const char * const disp_pwm_parents[] = { 337 "clk26m", 338 "univpll_d6_d4", 339 "osc_d2", 340 "osc_d4", 341 "osc_d16" 342 }; 343 344 static const char * const usb_top_parents[] = { 345 "clk26m", 346 "univpll_d5_d4", 347 "univpll_d6_d4", 348 "univpll_d5_d2" 349 }; 350 351 static const char * const ssusb_xhci_parents[] = { 352 "clk26m", 353 "univpll_d5_d4", 354 "univpll_d6_d4", 355 "univpll_d5_d2" 356 }; 357 358 static const char * const i2c_parents[] = { 359 "clk26m", 360 "mainpll_d4_d8", 361 "univpll_d5_d4" 362 }; 363 364 static const char * const seninf_parents[] = { 365 "clk26m", 366 "univpll_d4_d4", 367 "univpll_d6_d2", 368 "univpll_d4_d2", 369 "univpll_d7", 370 "univpll_d6", 371 "mmpll_d6", 372 "univpll_d5" 373 }; 374 375 static const char * const tl_parents[] = { 376 "clk26m", 377 "univpll_192m_d2", 378 "mainpll_d6_d4" 379 }; 380 381 static const char * const dxcc_parents[] = { 382 "clk26m", 383 "mainpll_d4_d2", 384 "mainpll_d4_d4", 385 "mainpll_d4_d8" 386 }; 387 388 static const char * const aud_engen1_parents[] = { 389 "clk26m", 390 "apll1_d2", 391 "apll1_d4", 392 "apll1_d8" 393 }; 394 395 static const char * const aud_engen2_parents[] = { 396 "clk26m", 397 "apll2_d2", 398 "apll2_d4", 399 "apll2_d8" 400 }; 401 402 static const char * const aes_ufsfde_parents[] = { 403 "clk26m", 404 "mainpll_d4", 405 "mainpll_d4_d2", 406 "mainpll_d6", 407 "mainpll_d4_d4", 408 "univpll_d4_d2", 409 "univpll_d6" 410 }; 411 412 static const char * const ufs_parents[] = { 413 "clk26m", 414 "mainpll_d4_d4", 415 "mainpll_d4_d8", 416 "univpll_d4_d4", 417 "mainpll_d6_d2", 418 "mainpll_d5_d2", 419 "msdcpll_d2" 420 }; 421 422 static const char * const aud_1_parents[] = { 423 "clk26m", 424 "apll1_ck" 425 }; 426 427 static const char * const aud_2_parents[] = { 428 "clk26m", 429 "apll2_ck" 430 }; 431 432 static const char * const adsp_parents[] = { 433 "clk26m", 434 "mainpll_d6", 435 "mainpll_d5_d2", 436 "univpll_d4_d4", 437 "univpll_d4", 438 "univpll_d6", 439 "ulposc", 440 "adsppll_ck" 441 }; 442 443 static const char * const dpmaif_main_parents[] = { 444 "clk26m", 445 "univpll_d4_d4", 446 "mainpll_d6", 447 "mainpll_d4_d2", 448 "univpll_d4_d2" 449 }; 450 451 static const char * const venc_parents[] = { 452 "clk26m", 453 "mmpll_d7", 454 "mainpll_d6", 455 "univpll_d4_d2", 456 "mainpll_d4_d2", 457 "univpll_d6", 458 "mmpll_d6", 459 "mainpll_d5_d2", 460 "mainpll_d6_d2", 461 "mmpll_d9", 462 "univpll_d4_d4", 463 "mainpll_d4", 464 "univpll_d4", 465 "univpll_d5", 466 "univpll_d5_d2", 467 "mainpll_d5" 468 }; 469 470 static const char * const vdec_parents[] = { 471 "clk26m", 472 "univpll_192m_d2", 473 "univpll_d5_d4", 474 "mainpll_d5", 475 "mainpll_d5_d2", 476 "mmpll_d6_d2", 477 "univpll_d5_d2", 478 "mainpll_d4_d2", 479 "univpll_d4_d2", 480 "univpll_d7", 481 "mmpll_d7", 482 "mmpll_d6", 483 "univpll_d5", 484 "mainpll_d4", 485 "univpll_d4", 486 "univpll_d6" 487 }; 488 489 static const char * const camtm_parents[] = { 490 "clk26m", 491 "univpll_d7", 492 "univpll_d6_d2", 493 "univpll_d4_d2" 494 }; 495 496 static const char * const pwm_parents[] = { 497 "clk26m", 498 "univpll_d4_d8" 499 }; 500 501 static const char * const audio_h_parents[] = { 502 "clk26m", 503 "univpll_d7", 504 "apll1_ck", 505 "apll2_ck" 506 }; 507 508 static const char * const spmi_mst_parents[] = { 509 "clk26m", 510 "csw_f26m_d2", 511 "osc_d8", 512 "osc_d10", 513 "osc_d16", 514 "osc_d20", 515 "clk32k" 516 }; 517 518 static const char * const aes_msdcfde_parents[] = { 519 "clk26m", 520 "mainpll_d4_d2", 521 "mainpll_d6", 522 "mainpll_d4_d4", 523 "univpll_d4_d2", 524 "univpll_d6" 525 }; 526 527 static const char * const sflash_parents[] = { 528 "clk26m", 529 "mainpll_d7_d8", 530 "univpll_d6_d8", 531 "univpll_d5_d8" 532 }; 533 534 static const char * const apll_i2s_m_parents[] = { 535 "aud_1_sel", 536 "aud_2_sel" 537 }; 538 539 /* 540 * CRITICAL CLOCK: 541 * axi_sel is the main bus clock of whole SOC. 542 * spm_sel is the clock of the always-on co-processor. 543 * bus_aximem_sel is clock of the bus that access emi. 544 */ 545 static const struct mtk_mux top_mtk_muxes[] = { 546 /* CLK_CFG_0 */ 547 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", 548 axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0, 549 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 550 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", 551 spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1, 552 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 553 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", 554 scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2), 555 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel", 556 bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3, 557 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 558 /* CLK_CFG_1 */ 559 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel", 560 disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4), 561 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel", 562 mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5), 563 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel", 564 img_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6), 565 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel", 566 img_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7), 567 /* CLK_CFG_2 */ 568 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel", 569 ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8), 570 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel", 571 dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9), 572 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel", 573 cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10), 574 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel", 575 ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11), 576 /* CLK_CFG_4 */ 577 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel", 578 dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16), 579 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", 580 mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18), 581 MUX_CLR_SET(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", mfg_pll_parents, 582 0x050, 0x054, 0x058, 18, 1), 583 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", 584 camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19), 585 /* CLK_CFG_5 */ 586 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel", 587 camtg_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20), 588 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", 589 camtg_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21), 590 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel", 591 camtg_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22), 592 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel", 593 camtg_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23), 594 /* CLK_CFG_6 */ 595 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel", 596 camtg_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24), 597 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", 598 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25), 599 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", 600 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26), 601 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", 602 msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 603 31, 0x004, 27, 0), 604 /* CLK_CFG_7 */ 605 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 606 msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28, 0), 607 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 608 msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29, 0), 609 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", 610 msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30, 0), 611 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", 612 audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0), 613 /* CLK_CFG_8 */ 614 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 615 aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1), 616 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel", 617 pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2), 618 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", 619 atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3), 620 /* CLK_CFG_9 */ 621 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel", 622 dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5), 623 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel", 624 scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6), 625 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 626 disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7), 627 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel", 628 usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8), 629 /* CLK_CFG_10 */ 630 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 631 ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9), 632 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", 633 i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10), 634 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", 635 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11), 636 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel", 637 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12), 638 /* CLK_CFG_11 */ 639 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel", 640 seninf_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13), 641 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel", 642 seninf_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14), 643 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel", 644 tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15), 645 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", 646 dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16), 647 /* CLK_CFG_12 */ 648 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 649 aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17), 650 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 651 aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18), 652 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel", 653 aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19), 654 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel", 655 ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20), 656 /* CLK_CFG_13 */ 657 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", 658 aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21), 659 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", 660 aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22), 661 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel", 662 adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23), 663 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel", 664 dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24), 665 /* CLK_CFG_14 */ 666 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel", 667 venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25), 668 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", 669 vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26), 670 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", 671 camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27), 672 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", 673 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28), 674 /* CLK_CFG_15 */ 675 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel", 676 audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29), 677 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel", 678 spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30), 679 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel", 680 aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1), 681 /* CLK_CFG_16 */ 682 MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel", 683 sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3), 684 }; 685 686 static struct mtk_composite top_muxes[] = { 687 /* CLK_AUDDIV_0 */ 688 MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s_m_parents, 0x320, 16, 1), 689 MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s_m_parents, 0x320, 17, 1), 690 MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s_m_parents, 0x320, 18, 1), 691 MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s_m_parents, 0x320, 19, 1), 692 MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s_m_parents, 0x320, 20, 1), 693 MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s_m_parents, 0x320, 21, 1), 694 MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s_m_parents, 0x320, 22, 1), 695 MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s_m_parents, 0x320, 23, 1), 696 MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s_m_parents, 0x320, 24, 1), 697 MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s_m_parents, 0x320, 25, 1), 698 /* APLL_DIV */ 699 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0), 700 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8), 701 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16), 702 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24), 703 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0), 704 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8), 705 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16), 706 DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24), 707 DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0), 708 DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8), 709 DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16), 710 }; 711 712 static const struct mtk_gate_regs infra0_cg_regs = { 713 .set_ofs = 0x80, 714 .clr_ofs = 0x84, 715 .sta_ofs = 0x90, 716 }; 717 718 static const struct mtk_gate_regs infra1_cg_regs = { 719 .set_ofs = 0x88, 720 .clr_ofs = 0x8c, 721 .sta_ofs = 0x94, 722 }; 723 724 static const struct mtk_gate_regs infra2_cg_regs = { 725 .set_ofs = 0xa4, 726 .clr_ofs = 0xa8, 727 .sta_ofs = 0xac, 728 }; 729 730 static const struct mtk_gate_regs infra3_cg_regs = { 731 .set_ofs = 0xc0, 732 .clr_ofs = 0xc4, 733 .sta_ofs = 0xc8, 734 }; 735 736 static const struct mtk_gate_regs infra4_cg_regs = { 737 .set_ofs = 0xd0, 738 .clr_ofs = 0xd4, 739 .sta_ofs = 0xd8, 740 }; 741 742 static const struct mtk_gate_regs infra5_cg_regs = { 743 .set_ofs = 0xe0, 744 .clr_ofs = 0xe4, 745 .sta_ofs = 0xe8, 746 }; 747 748 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 749 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 750 751 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \ 752 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \ 753 &mtk_clk_gate_ops_setclr, _flag) 754 755 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 756 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) 757 758 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 759 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 760 761 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \ 762 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \ 763 &mtk_clk_gate_ops_setclr, _flag) 764 765 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 766 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) 767 768 #define GATE_INFRA4(_id, _name, _parent, _shift) \ 769 GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 770 771 #define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \ 772 GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \ 773 &mtk_clk_gate_ops_setclr, _flag) 774 775 #define GATE_INFRA5(_id, _name, _parent, _shift) \ 776 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0) 777 778 /* 779 * CRITICAL CLOCK: 780 * infra_133m and infra_66m are main peripheral bus clocks of SOC. 781 * infra_device_apc and infra_device_apc_sync are for device access permission control module. 782 */ 783 static const struct mtk_gate infra_clks[] = { 784 /* INFRA0 */ 785 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0), 786 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1), 787 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2), 788 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3), 789 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4), 790 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5), 791 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 792 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8), 793 GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9), 794 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 795 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), 796 GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12), 797 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), 798 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), 799 GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15), 800 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16), 801 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17), 802 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18), 803 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19), 804 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), 805 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 806 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 807 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 808 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 809 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), 810 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28), 811 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 812 /* INFRA1 */ 813 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), 814 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2), 815 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4), 816 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5), 817 GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6), 818 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 819 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 820 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10), 821 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 822 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), 823 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), 824 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14), 825 GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15), 826 GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16), 827 GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17), 828 GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18), 829 GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19), 830 GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL), 831 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 832 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), 833 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 834 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 835 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), 836 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), 837 GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29), 838 GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30), 839 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31), 840 /* INFRA2 */ 841 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0), 842 GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1), 843 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2), 844 GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3), 845 GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4), 846 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5), 847 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), 848 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), 849 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), 850 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), 851 GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11), 852 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12), 853 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13), 854 GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14), 855 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), 856 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), 857 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), 858 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), 859 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), 860 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), 861 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), 862 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), 863 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), 864 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), 865 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27), 866 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28), 867 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29), 868 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30), 869 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31), 870 /* INFRA3 */ 871 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), 872 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), 873 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), 874 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), 875 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), 876 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7), 877 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8), 878 GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9), 879 GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10), 880 GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11), 881 GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14), 882 GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15), 883 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), 884 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), 885 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), 886 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), 887 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20), 888 GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21), 889 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), 890 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), 891 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), 892 GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25, 893 CLK_IS_CRITICAL), 894 GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26), 895 GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27), 896 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28), 897 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29), 898 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30), 899 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31), 900 /* INFRA4 */ 901 GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31), 902 /* INFRA5 */ 903 GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL), 904 GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL), 905 GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2), 906 GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3), 907 GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4), 908 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5), 909 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6), 910 GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30), 911 GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31), 912 }; 913 914 static const struct mtk_gate_regs peri_cg_regs = { 915 .set_ofs = 0x20c, 916 .clr_ofs = 0x20c, 917 .sta_ofs = 0x20c, 918 }; 919 920 #define GATE_PERI(_id, _name, _parent, _shift) \ 921 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 922 923 static const struct mtk_gate peri_clks[] = { 924 GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31), 925 }; 926 927 static const struct mtk_gate_regs top_cg_regs = { 928 .set_ofs = 0x150, 929 .clr_ofs = 0x150, 930 .sta_ofs = 0x150, 931 }; 932 933 #define GATE_TOP(_id, _name, _parent, _shift) \ 934 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 935 936 static const struct mtk_gate top_clks[] = { 937 GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24), 938 GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), 939 }; 940 941 static u16 infra_ao_rst_ofs[] = { 942 INFRA_RST0_SET_OFFSET, 943 INFRA_RST1_SET_OFFSET, 944 INFRA_RST2_SET_OFFSET, 945 INFRA_RST3_SET_OFFSET, 946 INFRA_RST4_SET_OFFSET, 947 }; 948 949 static u16 infra_ao_idx_map[] = { 950 [MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, 951 [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15, 952 [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, 953 [MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1, 954 [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12, 955 }; 956 957 static const struct mtk_clk_rst_desc clk_rst_desc = { 958 .version = MTK_RST_SET_CLR, 959 .rst_bank_ofs = infra_ao_rst_ofs, 960 .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), 961 .rst_idx_map = infra_ao_idx_map, 962 .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), 963 }; 964 965 /* Register mux notifier for MFG mux */ 966 static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) 967 { 968 struct mtk_mux_nb *mfg_mux_nb; 969 int i; 970 971 mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); 972 if (!mfg_mux_nb) 973 return -ENOMEM; 974 975 for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++) 976 if (top_mtk_muxes[i].id == CLK_TOP_MFG_PLL_SEL) 977 break; 978 if (i == ARRAY_SIZE(top_mtk_muxes)) 979 return -EINVAL; 980 981 mfg_mux_nb->ops = top_mtk_muxes[i].ops; 982 mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */ 983 984 return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); 985 } 986 987 static const struct mtk_clk_desc infra_desc = { 988 .clks = infra_clks, 989 .num_clks = ARRAY_SIZE(infra_clks), 990 .rst_desc = &clk_rst_desc, 991 }; 992 993 static const struct mtk_clk_desc peri_desc = { 994 .clks = peri_clks, 995 .num_clks = ARRAY_SIZE(peri_clks), 996 }; 997 998 static const struct mtk_clk_desc topck_desc = { 999 .fixed_clks = top_fixed_clks, 1000 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 1001 .factor_clks = top_divs, 1002 .num_factor_clks = ARRAY_SIZE(top_divs), 1003 .mux_clks = top_mtk_muxes, 1004 .num_mux_clks = ARRAY_SIZE(top_mtk_muxes), 1005 .composite_clks = top_muxes, 1006 .num_composite_clks = ARRAY_SIZE(top_muxes), 1007 .clks = top_clks, 1008 .num_clks = ARRAY_SIZE(top_clks), 1009 .clk_lock = &mt8192_clk_lock, 1010 .clk_notifier_func = clk_mt8192_reg_mfg_mux_notifier, 1011 .mfg_clk_idx = CLK_TOP_MFG_PLL_SEL, 1012 }; 1013 1014 static const struct of_device_id of_match_clk_mt8192[] = { 1015 { .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc }, 1016 { .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc }, 1017 { .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc }, 1018 { /* sentinel */ } 1019 }; 1020 MODULE_DEVICE_TABLE(of, of_match_clk_mt8192); 1021 1022 static struct platform_driver clk_mt8192_drv = { 1023 .driver = { 1024 .name = "clk-mt8192", 1025 .of_match_table = of_match_clk_mt8192, 1026 }, 1027 .probe = mtk_clk_simple_probe, 1028 .remove = mtk_clk_simple_remove, 1029 }; 1030 module_platform_driver(clk_mt8192_drv); 1031 1032 MODULE_DESCRIPTION("MediaTek MT8192 main clocks driver"); 1033 MODULE_LICENSE("GPL"); 1034