1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk-provider.h> 7 #include <linux/platform_device.h> 8 9 #include "clk-mtk.h" 10 #include "clk-gate.h" 11 12 #include <dt-bindings/clock/mt8192-clk.h> 13 14 static const struct mtk_gate_regs msdc_top_cg_regs = { 15 .set_ofs = 0x0, 16 .clr_ofs = 0x0, 17 .sta_ofs = 0x0, 18 }; 19 20 #define GATE_MSDC_TOP(_id, _name, _parent, _shift) \ 21 GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 22 23 static const struct mtk_gate msdc_top_clks[] = { 24 GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0), 25 GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1), 26 GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_1P, "msdc_top_src_1p", "infra_msdc1_src", 2), 27 GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_2P, "msdc_top_src_2p", "infra_msdc2_src", 3), 28 GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC0, "msdc_top_p_msdc0", "axi_sel", 4), 29 GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC1, "msdc_top_p_msdc1", "axi_sel", 5), 30 GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC2, "msdc_top_p_msdc2", "axi_sel", 6), 31 GATE_MSDC_TOP(CLK_MSDC_TOP_P_CFG, "msdc_top_p_cfg", "axi_sel", 7), 32 GATE_MSDC_TOP(CLK_MSDC_TOP_AXI, "msdc_top_axi", "axi_sel", 8), 33 GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_0P, "msdc_top_h_mst_0p", "infra_msdc0", 9), 34 GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_1P, "msdc_top_h_mst_1p", "infra_msdc1", 10), 35 GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_2P, "msdc_top_h_mst_2p", "infra_msdc2", 11), 36 GATE_MSDC_TOP(CLK_MSDC_TOP_MEM_OFF_DLY_26M, "msdc_top_mem_off_dly_26m", "clk26m", 12), 37 GATE_MSDC_TOP(CLK_MSDC_TOP_32K, "msdc_top_32k", "clk32k", 13), 38 GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14), 39 }; 40 41 static const struct mtk_clk_desc msdc_top_desc = { 42 .clks = msdc_top_clks, 43 .num_clks = ARRAY_SIZE(msdc_top_clks), 44 }; 45 46 static const struct of_device_id of_match_clk_mt8192_msdc[] = { 47 { 48 .compatible = "mediatek,mt8192-msdc_top", 49 .data = &msdc_top_desc, 50 }, { 51 /* sentinel */ 52 } 53 }; 54 MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_msdc); 55 56 static struct platform_driver clk_mt8192_msdc_drv = { 57 .probe = mtk_clk_simple_probe, 58 .remove = mtk_clk_simple_remove, 59 .driver = { 60 .name = "clk-mt8192-msdc", 61 .of_match_table = of_match_clk_mt8192_msdc, 62 }, 63 }; 64 module_platform_driver(clk_mt8192_msdc_drv); 65 66 MODULE_DESCRIPTION("MediaTek MT8192 MMC/SD Controller clocks driver"); 67 MODULE_LICENSE("GPL"); 68