1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk-provider.h> 7 #include <linux/of_device.h> 8 #include <linux/platform_device.h> 9 10 #include "clk-mtk.h" 11 #include "clk-gate.h" 12 13 #include <dt-bindings/clock/mt8192-clk.h> 14 15 static const struct mtk_gate_regs mfg_cg_regs = { 16 .set_ofs = 0x4, 17 .clr_ofs = 0x8, 18 .sta_ofs = 0x0, 19 }; 20 21 #define GATE_MFG(_id, _name, _parent, _shift) \ 22 GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 23 24 static const struct mtk_gate mfg_clks[] = { 25 GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0), 26 }; 27 28 static const struct mtk_clk_desc mfg_desc = { 29 .clks = mfg_clks, 30 .num_clks = ARRAY_SIZE(mfg_clks), 31 }; 32 33 static const struct of_device_id of_match_clk_mt8192_mfg[] = { 34 { 35 .compatible = "mediatek,mt8192-mfgcfg", 36 .data = &mfg_desc, 37 }, { 38 /* sentinel */ 39 } 40 }; 41 42 static struct platform_driver clk_mt8192_mfg_drv = { 43 .probe = mtk_clk_simple_probe, 44 .driver = { 45 .name = "clk-mt8192-mfg", 46 .of_match_table = of_match_clk_mt8192_mfg, 47 }, 48 }; 49 50 builtin_platform_driver(clk_mt8192_mfg_drv); 51