1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Garmin Chang <garmin.chang@mediatek.com> 5 */ 6 7 #include <dt-bindings/clock/mediatek,mt8188-clk.h> 8 #include <dt-bindings/reset/mt8188-resets.h> 9 #include <linux/clk-provider.h> 10 #include <linux/platform_device.h> 11 12 #include "clk-gate.h" 13 #include "clk-mtk.h" 14 15 static const struct mtk_gate_regs infra_ao0_cg_regs = { 16 .set_ofs = 0x80, 17 .clr_ofs = 0x84, 18 .sta_ofs = 0x90, 19 }; 20 21 static const struct mtk_gate_regs infra_ao1_cg_regs = { 22 .set_ofs = 0x88, 23 .clr_ofs = 0x8c, 24 .sta_ofs = 0x94, 25 }; 26 27 static const struct mtk_gate_regs infra_ao2_cg_regs = { 28 .set_ofs = 0xa4, 29 .clr_ofs = 0xa8, 30 .sta_ofs = 0xac, 31 }; 32 33 static const struct mtk_gate_regs infra_ao3_cg_regs = { 34 .set_ofs = 0xc0, 35 .clr_ofs = 0xc4, 36 .sta_ofs = 0xc8, 37 }; 38 39 static const struct mtk_gate_regs infra_ao4_cg_regs = { 40 .set_ofs = 0xe0, 41 .clr_ofs = 0xe4, 42 .sta_ofs = 0xe8, 43 }; 44 45 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ 46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \ 47 &mtk_clk_gate_ops_setclr, _flag) 48 49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ 50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0) 51 52 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ 53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \ 54 &mtk_clk_gate_ops_setclr, _flag) 55 56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ 57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0) 58 59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ 60 GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 61 62 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ 63 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \ 64 &mtk_clk_gate_ops_setclr, _flag) 65 66 #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \ 67 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \ 68 &mtk_clk_gate_ops_setclr, _flag) 69 70 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ 71 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0) 72 73 #define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \ 74 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \ 75 &mtk_clk_gate_ops_setclr, _flag) 76 77 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ 78 GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0) 79 80 static const struct mtk_gate infra_ao_clks[] = { 81 /* INFRA_AO0 */ 82 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0), 83 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1), 84 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2), 85 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3), 86 /* infra_ao_sej is main clock is for secure engine with JTAG support */ 87 GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL), 88 GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6), 89 GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8), 90 GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9), 91 GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10), 92 GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_h", "top_axi", 15), 93 GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16), 94 GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17), 95 GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18), 96 GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19), 97 GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21), 98 GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22), 99 GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23), 100 GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24), 101 GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25), 102 GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26), 103 GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27), 104 GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "pad_fpc_ck", 28), 105 GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29), 106 /* INFRA_AO1 */ 107 GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0), 108 GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1), 109 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2), 110 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4), 111 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, "infra_ao_msdc2", "top_axi", 5), 112 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 6), 113 /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */ 114 GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC, "infra_ao_dvfsrc", 115 "clk26m", 7, CLK_IS_CRITICAL), 116 GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9), 117 GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10), 118 GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11), 119 GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12), 120 GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, "infra_ao_cec_66m_hclk", "top_axi", 13), 121 GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15), 122 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 16), 123 GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, "infra_ao_cec_66m_bclk", "top_axi", 17), 124 GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18), 125 /* infra_ao_dapc is for device access permission control module */ 126 GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_dapc", 127 "top_axi", 20, CLK_IS_CRITICAL), 128 GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, "infra_ao_ecc_66m_hclk", "top_axi", 23), 129 GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24), 130 GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25), 131 GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26), 132 GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29), 133 GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31), 134 /* INFRA_AO2 */ 135 GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0), 136 GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2), 137 GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3), 138 GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4), 139 GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6), 140 GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9), 141 GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10), 142 GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_FSSPM, "infra_ao_fsspm", 143 "top_sspm", 15, CLK_IS_CRITICAL), 144 GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM_BUS_HCLK, "infra_ao_sspm_hclk", 145 "top_axi", 17, CLK_IS_CRITICAL), 146 GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_BCLK, "infra_ao_apdma_bclk", "top_axi", 18), 147 GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25), 148 GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26), 149 GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27), 150 /* INFRA_AO3 */ 151 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0), 152 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1sf", "top_msdc50_0", 1), 153 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2sf", "top_msdc50_0", 2), 154 GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5), 155 GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7), 156 GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8), 157 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, "infra_ao_msdc30_2", "top_msdc30_2", 9), 158 GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10), 159 GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15), 160 GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, "infra_ao_gcpu_66m_bclk", "top_axi", 16), 161 GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, "infra_ao_gcpu_133m_bclk", "top_axi", 17), 162 GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20), 163 GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24), 164 /* infra_ao_dapc_sync is for device access permission control module */ 165 GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_dapc_sync", 166 "top_axi", 25, CLK_IS_CRITICAL), 167 GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26), 168 /* INFRA_AO4 */ 169 /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */ 170 GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_MCLK_CK, "infra_ao_133m_mclk_set", 171 "top_axi", 0, CLK_IS_CRITICAL), 172 GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_MCLK_CK, "infra_ao_66m_mclk_set", 173 "top_axi", 1, CLK_IS_CRITICAL), 174 GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", 175 "pextp_pipe", 7), 176 GATE_INFRA_AO4(CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P, 177 "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), 178 }; 179 180 static u16 infra_ao_rst_ofs[] = { 181 INFRA_RST0_SET_OFFSET, 182 INFRA_RST1_SET_OFFSET, 183 INFRA_RST2_SET_OFFSET, 184 INFRA_RST3_SET_OFFSET, 185 INFRA_RST4_SET_OFFSET, 186 }; 187 188 static u16 infra_ao_idx_map[] = { 189 [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2, 190 [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4, 191 [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5, 192 }; 193 194 static const struct mtk_clk_rst_desc infra_ao_rst_desc = { 195 .version = MTK_RST_SET_CLR, 196 .rst_bank_ofs = infra_ao_rst_ofs, 197 .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), 198 .rst_idx_map = infra_ao_idx_map, 199 .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), 200 }; 201 202 static const struct mtk_clk_desc infra_ao_desc = { 203 .clks = infra_ao_clks, 204 .num_clks = ARRAY_SIZE(infra_ao_clks), 205 .rst_desc = &infra_ao_rst_desc, 206 }; 207 208 static const struct of_device_id of_match_clk_mt8188_infra_ao[] = { 209 { .compatible = "mediatek,mt8188-infracfg-ao", .data = &infra_ao_desc }, 210 { /* sentinel */ } 211 }; 212 MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_infra_ao); 213 214 static struct platform_driver clk_mt8188_infra_ao_drv = { 215 .probe = mtk_clk_simple_probe, 216 .remove_new = mtk_clk_simple_remove, 217 .driver = { 218 .name = "clk-mt8188-infra_ao", 219 .of_match_table = of_match_clk_mt8188_infra_ao, 220 }, 221 }; 222 module_platform_driver(clk_mt8188_infra_ao_drv); 223 MODULE_LICENSE("GPL"); 224