1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 6 #include <linux/delay.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 14 #include "clk-mtk.h" 15 #include "clk-mux.h" 16 #include "clk-gate.h" 17 18 #include <dt-bindings/clock/mt8183-clk.h> 19 20 static DEFINE_SPINLOCK(mt8183_clk_lock); 21 22 static const struct mtk_fixed_clk top_fixed_clks[] = { 23 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 24 FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 25 FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 26 }; 27 28 static const struct mtk_fixed_factor top_early_divs[] = { 29 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), 30 }; 31 32 static const struct mtk_fixed_factor top_divs[] = { 33 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 34 2), 35 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 36 1), 37 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 38 2), 39 FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 40 2), 41 FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 42 4), 43 FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 44 8), 45 FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 46 16), 47 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 48 3), 49 FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 50 2), 51 FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 52 4), 53 FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 54 8), 55 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 56 5), 57 FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 58 2), 59 FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 60 4), 61 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 62 7), 63 FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 64 2), 65 FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 66 4), 67 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 68 1), 69 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 70 2), 71 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 72 2), 73 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 74 4), 75 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 76 8), 77 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 78 3), 79 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 80 2), 81 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 82 4), 83 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 84 8), 85 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 86 5), 87 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 88 2), 89 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 90 4), 91 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 92 8), 93 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 94 7), 95 FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 96 1), 97 FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 98 2), 99 FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 100 4), 101 FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 102 8), 103 FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 104 16), 105 FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 106 32), 107 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 108 1), 109 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 110 2), 111 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 112 4), 113 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 114 8), 115 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 116 1), 117 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 118 2), 119 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 120 4), 121 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 122 8), 123 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 124 1), 125 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 126 2), 127 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 128 4), 129 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 130 8), 131 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 132 16), 133 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 134 1), 135 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 136 4), 137 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 138 2), 139 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 140 4), 141 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 142 5), 143 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 144 2), 145 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 146 4), 147 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 148 6), 149 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 150 7), 151 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 152 1), 153 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 154 1), 155 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 156 2), 157 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 158 4), 159 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 160 8), 161 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 162 16), 163 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 164 1), 165 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 166 2), 167 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 168 4), 169 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 170 8), 171 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 172 16), 173 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 174 2), 175 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 176 16), 177 }; 178 179 static const char * const axi_parents[] = { 180 "clk26m", 181 "syspll_d2_d4", 182 "syspll_d7", 183 "osc_d4" 184 }; 185 186 static const char * const mm_parents[] = { 187 "clk26m", 188 "mmpll_d7", 189 "syspll_d3", 190 "univpll_d2_d2", 191 "syspll_d2_d2", 192 "syspll_d3_d2" 193 }; 194 195 static const char * const img_parents[] = { 196 "clk26m", 197 "mmpll_d6", 198 "univpll_d3", 199 "syspll_d3", 200 "univpll_d2_d2", 201 "syspll_d2_d2", 202 "univpll_d3_d2", 203 "syspll_d3_d2" 204 }; 205 206 static const char * const cam_parents[] = { 207 "clk26m", 208 "syspll_d2", 209 "mmpll_d6", 210 "syspll_d3", 211 "mmpll_d7", 212 "univpll_d3", 213 "univpll_d2_d2", 214 "syspll_d2_d2", 215 "syspll_d3_d2", 216 "univpll_d3_d2" 217 }; 218 219 static const char * const dsp_parents[] = { 220 "clk26m", 221 "mmpll_d6", 222 "mmpll_d7", 223 "univpll_d3", 224 "syspll_d3", 225 "univpll_d2_d2", 226 "syspll_d2_d2", 227 "univpll_d3_d2", 228 "syspll_d3_d2" 229 }; 230 231 static const char * const dsp1_parents[] = { 232 "clk26m", 233 "mmpll_d6", 234 "mmpll_d7", 235 "univpll_d3", 236 "syspll_d3", 237 "univpll_d2_d2", 238 "syspll_d2_d2", 239 "univpll_d3_d2", 240 "syspll_d3_d2" 241 }; 242 243 static const char * const dsp2_parents[] = { 244 "clk26m", 245 "mmpll_d6", 246 "mmpll_d7", 247 "univpll_d3", 248 "syspll_d3", 249 "univpll_d2_d2", 250 "syspll_d2_d2", 251 "univpll_d3_d2", 252 "syspll_d3_d2" 253 }; 254 255 static const char * const ipu_if_parents[] = { 256 "clk26m", 257 "mmpll_d6", 258 "mmpll_d7", 259 "univpll_d3", 260 "syspll_d3", 261 "univpll_d2_d2", 262 "syspll_d2_d2", 263 "univpll_d3_d2", 264 "syspll_d3_d2" 265 }; 266 267 static const char * const mfg_parents[] = { 268 "clk26m", 269 "mfgpll_ck", 270 "univpll_d3", 271 "syspll_d3" 272 }; 273 274 static const char * const f52m_mfg_parents[] = { 275 "clk26m", 276 "univpll_d3_d2", 277 "univpll_d3_d4", 278 "univpll_d3_d8" 279 }; 280 281 static const char * const camtg_parents[] = { 282 "clk26m", 283 "univ_192m_d8", 284 "univpll_d3_d8", 285 "univ_192m_d4", 286 "univpll_d3_d16", 287 "csw_f26m_ck_d2", 288 "univ_192m_d16", 289 "univ_192m_d32" 290 }; 291 292 static const char * const camtg2_parents[] = { 293 "clk26m", 294 "univ_192m_d8", 295 "univpll_d3_d8", 296 "univ_192m_d4", 297 "univpll_d3_d16", 298 "csw_f26m_ck_d2", 299 "univ_192m_d16", 300 "univ_192m_d32" 301 }; 302 303 static const char * const camtg3_parents[] = { 304 "clk26m", 305 "univ_192m_d8", 306 "univpll_d3_d8", 307 "univ_192m_d4", 308 "univpll_d3_d16", 309 "csw_f26m_ck_d2", 310 "univ_192m_d16", 311 "univ_192m_d32" 312 }; 313 314 static const char * const camtg4_parents[] = { 315 "clk26m", 316 "univ_192m_d8", 317 "univpll_d3_d8", 318 "univ_192m_d4", 319 "univpll_d3_d16", 320 "csw_f26m_ck_d2", 321 "univ_192m_d16", 322 "univ_192m_d32" 323 }; 324 325 static const char * const uart_parents[] = { 326 "clk26m", 327 "univpll_d3_d8" 328 }; 329 330 static const char * const spi_parents[] = { 331 "clk26m", 332 "syspll_d5_d2", 333 "syspll_d3_d4", 334 "msdcpll_d4" 335 }; 336 337 static const char * const msdc50_hclk_parents[] = { 338 "clk26m", 339 "syspll_d2_d2", 340 "syspll_d3_d2" 341 }; 342 343 static const char * const msdc50_0_parents[] = { 344 "clk26m", 345 "msdcpll_ck", 346 "msdcpll_d2", 347 "univpll_d2_d4", 348 "syspll_d3_d2", 349 "univpll_d2_d2" 350 }; 351 352 static const char * const msdc30_1_parents[] = { 353 "clk26m", 354 "univpll_d3_d2", 355 "syspll_d3_d2", 356 "syspll_d7", 357 "msdcpll_d2" 358 }; 359 360 static const char * const msdc30_2_parents[] = { 361 "clk26m", 362 "univpll_d3_d2", 363 "syspll_d3_d2", 364 "syspll_d7", 365 "msdcpll_d2" 366 }; 367 368 static const char * const audio_parents[] = { 369 "clk26m", 370 "syspll_d5_d4", 371 "syspll_d7_d4", 372 "syspll_d2_d16" 373 }; 374 375 static const char * const aud_intbus_parents[] = { 376 "clk26m", 377 "syspll_d2_d4", 378 "syspll_d7_d2" 379 }; 380 381 static const char * const pmicspi_parents[] = { 382 "clk26m", 383 "syspll_d2_d8", 384 "osc_d8" 385 }; 386 387 static const char * const fpwrap_ulposc_parents[] = { 388 "clk26m", 389 "osc_d16", 390 "osc_d4", 391 "osc_d8" 392 }; 393 394 static const char * const atb_parents[] = { 395 "clk26m", 396 "syspll_d2_d2", 397 "syspll_d5" 398 }; 399 400 static const char * const dpi0_parents[] = { 401 "clk26m", 402 "tvdpll_d2", 403 "tvdpll_d4", 404 "tvdpll_d8", 405 "tvdpll_d16", 406 "univpll_d5_d2", 407 "univpll_d3_d4", 408 "syspll_d3_d4", 409 "univpll_d3_d8" 410 }; 411 412 static const char * const scam_parents[] = { 413 "clk26m", 414 "syspll_d5_d2" 415 }; 416 417 static const char * const disppwm_parents[] = { 418 "clk26m", 419 "univpll_d3_d4", 420 "osc_d2", 421 "osc_d4", 422 "osc_d16" 423 }; 424 425 static const char * const usb_top_parents[] = { 426 "clk26m", 427 "univpll_d5_d4", 428 "univpll_d3_d4", 429 "univpll_d5_d2" 430 }; 431 432 433 static const char * const ssusb_top_xhci_parents[] = { 434 "clk26m", 435 "univpll_d5_d4", 436 "univpll_d3_d4", 437 "univpll_d5_d2" 438 }; 439 440 static const char * const spm_parents[] = { 441 "clk26m", 442 "syspll_d2_d8" 443 }; 444 445 static const char * const i2c_parents[] = { 446 "clk26m", 447 "syspll_d2_d8", 448 "univpll_d5_d2" 449 }; 450 451 static const char * const scp_parents[] = { 452 "clk26m", 453 "univpll_d2_d8", 454 "syspll_d5", 455 "syspll_d2_d2", 456 "univpll_d2_d2", 457 "syspll_d3", 458 "univpll_d3" 459 }; 460 461 static const char * const seninf_parents[] = { 462 "clk26m", 463 "univpll_d2_d2", 464 "univpll_d3_d2", 465 "univpll_d2_d4" 466 }; 467 468 static const char * const dxcc_parents[] = { 469 "clk26m", 470 "syspll_d2_d2", 471 "syspll_d2_d4", 472 "syspll_d2_d8" 473 }; 474 475 static const char * const aud_engen1_parents[] = { 476 "clk26m", 477 "apll1_d2", 478 "apll1_d4", 479 "apll1_d8" 480 }; 481 482 static const char * const aud_engen2_parents[] = { 483 "clk26m", 484 "apll2_d2", 485 "apll2_d4", 486 "apll2_d8" 487 }; 488 489 static const char * const faes_ufsfde_parents[] = { 490 "clk26m", 491 "syspll_d2", 492 "syspll_d2_d2", 493 "syspll_d3", 494 "syspll_d2_d4", 495 "univpll_d3" 496 }; 497 498 static const char * const fufs_parents[] = { 499 "clk26m", 500 "syspll_d2_d4", 501 "syspll_d2_d8", 502 "syspll_d2_d16" 503 }; 504 505 static const char * const aud_1_parents[] = { 506 "clk26m", 507 "apll1_ck" 508 }; 509 510 static const char * const aud_2_parents[] = { 511 "clk26m", 512 "apll2_ck" 513 }; 514 515 /* 516 * CRITICAL CLOCK: 517 * axi_sel is the main bus clock of whole SOC. 518 * spm_sel is the clock of the always-on co-processor. 519 */ 520 static const struct mtk_mux top_muxes[] = { 521 /* CLK_CFG_0 */ 522 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 523 axi_parents, 0x40, 524 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), 525 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 526 mm_parents, 0x40, 527 0x44, 0x48, 8, 3, 15, 0x004, 1), 528 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 529 img_parents, 0x40, 530 0x44, 0x48, 16, 3, 23, 0x004, 2), 531 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 532 cam_parents, 0x40, 533 0x44, 0x48, 24, 4, 31, 0x004, 3), 534 /* CLK_CFG_1 */ 535 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 536 dsp_parents, 0x50, 537 0x54, 0x58, 0, 4, 7, 0x004, 4), 538 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 539 dsp1_parents, 0x50, 540 0x54, 0x58, 8, 4, 15, 0x004, 5), 541 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 542 dsp2_parents, 0x50, 543 0x54, 0x58, 16, 4, 23, 0x004, 6), 544 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 545 ipu_if_parents, 0x50, 546 0x54, 0x58, 24, 4, 31, 0x004, 7), 547 /* CLK_CFG_2 */ 548 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 549 mfg_parents, 0x60, 550 0x64, 0x68, 0, 2, 7, 0x004, 8), 551 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 552 f52m_mfg_parents, 0x60, 553 0x64, 0x68, 8, 2, 15, 0x004, 9), 554 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 555 camtg_parents, 0x60, 556 0x64, 0x68, 16, 3, 23, 0x004, 10), 557 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 558 camtg2_parents, 0x60, 559 0x64, 0x68, 24, 3, 31, 0x004, 11), 560 /* CLK_CFG_3 */ 561 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 562 camtg3_parents, 0x70, 563 0x74, 0x78, 0, 3, 7, 0x004, 12), 564 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 565 camtg4_parents, 0x70, 566 0x74, 0x78, 8, 3, 15, 0x004, 13), 567 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 568 uart_parents, 0x70, 569 0x74, 0x78, 16, 1, 23, 0x004, 14), 570 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 571 spi_parents, 0x70, 572 0x74, 0x78, 24, 2, 31, 0x004, 15), 573 /* CLK_CFG_4 */ 574 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 575 msdc50_hclk_parents, 0x80, 576 0x84, 0x88, 0, 2, 7, 0x004, 16), 577 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 578 msdc50_0_parents, 0x80, 579 0x84, 0x88, 8, 3, 15, 0x004, 17), 580 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 581 msdc30_1_parents, 0x80, 582 0x84, 0x88, 16, 3, 23, 0x004, 18), 583 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 584 msdc30_2_parents, 0x80, 585 0x84, 0x88, 24, 3, 31, 0x004, 19), 586 /* CLK_CFG_5 */ 587 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 588 audio_parents, 0x90, 589 0x94, 0x98, 0, 2, 7, 0x004, 20), 590 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 591 aud_intbus_parents, 0x90, 592 0x94, 0x98, 8, 2, 15, 0x004, 21), 593 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 594 pmicspi_parents, 0x90, 595 0x94, 0x98, 16, 2, 23, 0x004, 22), 596 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 597 fpwrap_ulposc_parents, 0x90, 598 0x94, 0x98, 24, 2, 31, 0x004, 23), 599 /* CLK_CFG_6 */ 600 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 601 atb_parents, 0xa0, 602 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 603 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 604 dpi0_parents, 0xa0, 605 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 606 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 607 scam_parents, 0xa0, 608 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 609 /* CLK_CFG_7 */ 610 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 611 disppwm_parents, 0xb0, 612 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 613 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 614 usb_top_parents, 0xb0, 615 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 616 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 617 ssusb_top_xhci_parents, 0xb0, 618 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 619 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 620 spm_parents, 0xb0, 621 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), 622 /* CLK_CFG_8 */ 623 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 624 i2c_parents, 0xc0, 625 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 626 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 627 scp_parents, 0xc0, 628 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 629 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 630 seninf_parents, 0xc0, 631 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 632 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 633 dxcc_parents, 0xc0, 634 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 635 /* CLK_CFG_9 */ 636 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 637 aud_engen1_parents, 0xd0, 638 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 639 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 640 aud_engen2_parents, 0xd0, 641 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 642 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 643 faes_ufsfde_parents, 0xd0, 644 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 645 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 646 fufs_parents, 0xd0, 647 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 648 /* CLK_CFG_10 */ 649 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 650 aud_1_parents, 0xe0, 651 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 652 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 653 aud_2_parents, 0xe0, 654 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 655 }; 656 657 static const char * const apll_i2s0_parents[] = { 658 "aud_1_sel", 659 "aud_2_sel" 660 }; 661 662 static const char * const apll_i2s1_parents[] = { 663 "aud_1_sel", 664 "aud_2_sel" 665 }; 666 667 static const char * const apll_i2s2_parents[] = { 668 "aud_1_sel", 669 "aud_2_sel" 670 }; 671 672 static const char * const apll_i2s3_parents[] = { 673 "aud_1_sel", 674 "aud_2_sel" 675 }; 676 677 static const char * const apll_i2s4_parents[] = { 678 "aud_1_sel", 679 "aud_2_sel" 680 }; 681 682 static const char * const apll_i2s5_parents[] = { 683 "aud_1_sel", 684 "aud_2_sel" 685 }; 686 687 static struct mtk_composite top_aud_muxes[] = { 688 MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 689 0x320, 8, 1), 690 MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 691 0x320, 9, 1), 692 MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 693 0x320, 10, 1), 694 MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 695 0x320, 11, 1), 696 MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 697 0x320, 12, 1), 698 MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 699 0x328, 20, 1), 700 }; 701 702 static const char * const mcu_mp0_parents[] = { 703 "clk26m", 704 "armpll_ll", 705 "armpll_div_pll1", 706 "armpll_div_pll2" 707 }; 708 709 static const char * const mcu_mp2_parents[] = { 710 "clk26m", 711 "armpll_l", 712 "armpll_div_pll1", 713 "armpll_div_pll2" 714 }; 715 716 static const char * const mcu_bus_parents[] = { 717 "clk26m", 718 "ccipll", 719 "armpll_div_pll1", 720 "armpll_div_pll2" 721 }; 722 723 static struct mtk_composite mcu_muxes[] = { 724 /* mp0_pll_divider_cfg */ 725 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 726 /* mp2_pll_divider_cfg */ 727 MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 728 /* bus_pll_divider_cfg */ 729 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 730 }; 731 732 static struct mtk_composite top_aud_divs[] = { 733 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 734 0x320, 2, 0x324, 8, 0), 735 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 736 0x320, 3, 0x324, 8, 8), 737 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 738 0x320, 4, 0x324, 8, 16), 739 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 740 0x320, 5, 0x324, 8, 24), 741 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 742 0x320, 6, 0x328, 8, 0), 743 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 744 0x320, 7, 0x328, 8, 8), 745 }; 746 747 static const struct mtk_gate_regs top_cg_regs = { 748 .set_ofs = 0x104, 749 .clr_ofs = 0x104, 750 .sta_ofs = 0x104, 751 }; 752 753 #define GATE_TOP(_id, _name, _parent, _shift) \ 754 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 755 &mtk_clk_gate_ops_no_setclr_inv) 756 757 static const struct mtk_gate top_clks[] = { 758 /* TOP */ 759 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 760 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 761 }; 762 763 static const struct mtk_gate_regs infra0_cg_regs = { 764 .set_ofs = 0x80, 765 .clr_ofs = 0x84, 766 .sta_ofs = 0x90, 767 }; 768 769 static const struct mtk_gate_regs infra1_cg_regs = { 770 .set_ofs = 0x88, 771 .clr_ofs = 0x8c, 772 .sta_ofs = 0x94, 773 }; 774 775 static const struct mtk_gate_regs infra2_cg_regs = { 776 .set_ofs = 0xa4, 777 .clr_ofs = 0xa8, 778 .sta_ofs = 0xac, 779 }; 780 781 static const struct mtk_gate_regs infra3_cg_regs = { 782 .set_ofs = 0xc0, 783 .clr_ofs = 0xc4, 784 .sta_ofs = 0xc8, 785 }; 786 787 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 788 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 789 &mtk_clk_gate_ops_setclr) 790 791 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 792 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 793 &mtk_clk_gate_ops_setclr) 794 795 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 796 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 797 &mtk_clk_gate_ops_setclr) 798 799 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 800 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 801 &mtk_clk_gate_ops_setclr) 802 803 static const struct mtk_gate infra_clks[] = { 804 /* INFRA0 */ 805 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 806 "axi_sel", 0), 807 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 808 "axi_sel", 1), 809 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 810 "axi_sel", 2), 811 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", 812 "axi_sel", 3), 813 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", 814 "scp_sel", 4), 815 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", 816 "f_f26m_ck", 5), 817 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", 818 "axi_sel", 6), 819 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", 820 "axi_sel", 8), 821 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", 822 "axi_sel", 9), 823 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", 824 "axi_sel", 10), 825 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", 826 "i2c_sel", 11), 827 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", 828 "i2c_sel", 12), 829 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", 830 "i2c_sel", 13), 831 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", 832 "i2c_sel", 14), 833 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", 834 "axi_sel", 15), 835 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", 836 "i2c_sel", 16), 837 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", 838 "i2c_sel", 17), 839 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", 840 "i2c_sel", 18), 841 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", 842 "i2c_sel", 19), 843 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 844 "i2c_sel", 21), 845 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 846 "uart_sel", 22), 847 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 848 "uart_sel", 23), 849 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", 850 "uart_sel", 24), 851 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", 852 "uart_sel", 25), 853 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", 854 "axi_sel", 27), 855 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", 856 "axi_sel", 28), 857 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", 858 "axi_sel", 31), 859 /* INFRA1 */ 860 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", 861 "spi_sel", 1), 862 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", 863 "msdc50_hclk_sel", 2), 864 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", 865 "axi_sel", 4), 866 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", 867 "axi_sel", 5), 868 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", 869 "msdc50_0_sel", 6), 870 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", 871 "f_f26m_ck", 7), 872 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", 873 "axi_sel", 8), 874 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", 875 "axi_sel", 9), 876 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", 877 "f_f26m_ck", 10), 878 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", 879 "axi_sel", 11), 880 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", 881 "axi_sel", 12), 882 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", 883 "axi_sel", 13), 884 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", 885 "f_f26m_ck", 14), 886 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", 887 "msdc30_1_sel", 16), 888 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", 889 "msdc30_2_sel", 17), 890 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", 891 "axi_sel", 18), 892 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", 893 "axi_sel", 19), 894 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", 895 "axi_sel", 20), 896 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", 897 "axi_sel", 23), 898 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", 899 "axi_sel", 24), 900 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", 901 "axi_sel", 25), 902 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", 903 "axi_sel", 26), 904 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", 905 "dxcc_sel", 27), 906 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", 907 "dxcc_sel", 28), 908 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", 909 "axi_sel", 30), 910 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 911 "f_f26m_ck", 31), 912 /* INFRA2 */ 913 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", 914 "f_f26m_ck", 0), 915 GATE_INFRA2(CLK_INFRA_USB, "infra_usb", 916 "usb_top_sel", 1), 917 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", 918 "axi_sel", 2), 919 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", 920 "axi_sel", 3), 921 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", 922 "f_f26m_ck", 4), 923 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", 924 "spi_sel", 6), 925 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", 926 "i2c_sel", 7), 927 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", 928 "f_f26m_ck", 8), 929 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", 930 "spi_sel", 9), 931 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", 932 "spi_sel", 10), 933 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", 934 "ssusb_top_xhci_sel", 11), 935 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", 936 "fufs_sel", 12), 937 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", 938 "fufs_sel", 13), 939 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", 940 "axi_sel", 14), 941 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", 942 "axi_sel", 16), 943 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", 944 "i2c_sel", 18), 945 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", 946 "i2c_sel", 19), 947 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", 948 "i2c_sel", 20), 949 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", 950 "i2c_sel", 21), 951 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", 952 "i2c_sel", 22), 953 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", 954 "i2c_sel", 23), 955 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", 956 "i2c_sel", 24), 957 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", 958 "spi_sel", 25), 959 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", 960 "spi_sel", 26), 961 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", 962 "axi_sel", 27), 963 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", 964 "fufs_sel", 28), 965 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", 966 "faes_ufsfde_sel", 29), 967 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", 968 "fufs_sel", 30), 969 /* INFRA3 */ 970 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", 971 "msdc50_0_sel", 0), 972 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", 973 "msdc50_0_sel", 1), 974 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", 975 "msdc50_0_sel", 2), 976 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", 977 "axi_sel", 5), 978 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", 979 "i2c_sel", 6), 980 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", 981 "msdc50_hclk_sel", 7), 982 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", 983 "msdc50_hclk_sel", 8), 984 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", 985 "axi_sel", 16), 986 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", 987 "axi_sel", 17), 988 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", 989 "axi_sel", 18), 990 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", 991 "axi_sel", 19), 992 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", 993 "f_f26m_ck", 20), 994 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", 995 "axi_sel", 21), 996 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", 997 "i2c_sel", 22), 998 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", 999 "i2c_sel", 23), 1000 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", 1001 "msdc50_0_sel", 24), 1002 }; 1003 1004 static const struct mtk_gate_regs apmixed_cg_regs = { 1005 .set_ofs = 0x20, 1006 .clr_ofs = 0x20, 1007 .sta_ofs = 0x20, 1008 }; 1009 1010 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ 1011 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ 1012 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) 1013 1014 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 1015 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) 1016 1017 /* 1018 * CRITICAL CLOCK: 1019 * apmixed_appll26m is the toppest clock gate of all PLLs. 1020 */ 1021 static const struct mtk_gate apmixed_clks[] = { 1022 /* AUDIO0 */ 1023 GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", 1024 "f_f26m_ck", 4), 1025 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", 1026 "f_f26m_ck", 5, CLK_IS_CRITICAL), 1027 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", 1028 "f_f26m_ck", 6), 1029 GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", 1030 "f_f26m_ck", 7), 1031 GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", 1032 "f_f26m_ck", 8), 1033 GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", 1034 "f_f26m_ck", 9), 1035 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", 1036 "f_f26m_ck", 11), 1037 GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", 1038 "f_f26m_ck", 13), 1039 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 1040 "f_f26m_ck", 14), 1041 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", 1042 "f_f26m_ck", 16), 1043 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", 1044 "f_f26m_ck", 17), 1045 }; 1046 1047 #define MT8183_PLL_FMAX (3800UL * MHZ) 1048 #define MT8183_PLL_FMIN (1500UL * MHZ) 1049 1050 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1051 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1052 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1053 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1054 _pcw_chg_reg, _div_table) { \ 1055 .id = _id, \ 1056 .name = _name, \ 1057 .reg = _reg, \ 1058 .pwr_reg = _pwr_reg, \ 1059 .en_mask = _en_mask, \ 1060 .flags = _flags, \ 1061 .rst_bar_mask = _rst_bar_mask, \ 1062 .fmax = MT8183_PLL_FMAX, \ 1063 .fmin = MT8183_PLL_FMIN, \ 1064 .pcwbits = _pcwbits, \ 1065 .pcwibits = _pcwibits, \ 1066 .pd_reg = _pd_reg, \ 1067 .pd_shift = _pd_shift, \ 1068 .tuner_reg = _tuner_reg, \ 1069 .tuner_en_reg = _tuner_en_reg, \ 1070 .tuner_en_bit = _tuner_en_bit, \ 1071 .pcw_reg = _pcw_reg, \ 1072 .pcw_shift = _pcw_shift, \ 1073 .pcw_chg_reg = _pcw_chg_reg, \ 1074 .div_table = _div_table, \ 1075 } 1076 1077 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1078 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1079 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1080 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1081 _pcw_chg_reg) \ 1082 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1083 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1084 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1085 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1086 _pcw_chg_reg, NULL) 1087 1088 static const struct mtk_pll_div_table armpll_div_table[] = { 1089 { .div = 0, .freq = MT8183_PLL_FMAX }, 1090 { .div = 1, .freq = 1500 * MHZ }, 1091 { .div = 2, .freq = 750 * MHZ }, 1092 { .div = 3, .freq = 375 * MHZ }, 1093 { .div = 4, .freq = 187500000 }, 1094 { } /* sentinel */ 1095 }; 1096 1097 static const struct mtk_pll_div_table mfgpll_div_table[] = { 1098 { .div = 0, .freq = MT8183_PLL_FMAX }, 1099 { .div = 1, .freq = 1600 * MHZ }, 1100 { .div = 2, .freq = 800 * MHZ }, 1101 { .div = 3, .freq = 400 * MHZ }, 1102 { .div = 4, .freq = 200 * MHZ }, 1103 { } /* sentinel */ 1104 }; 1105 1106 static const struct mtk_pll_data plls[] = { 1107 PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001, 1108 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, 1109 0x0204, 0, 0, armpll_div_table), 1110 PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001, 1111 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, 1112 0x0214, 0, 0, armpll_div_table), 1113 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001, 1114 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, 1115 0x0294, 0, 0), 1116 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001, 1117 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, 1118 0x0224, 0, 0), 1119 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001, 1120 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, 1121 0x0234, 0, 0), 1122 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001, 1123 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, 1124 mfgpll_div_table), 1125 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001, 1126 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), 1127 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001, 1128 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), 1129 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001, 1130 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, 1131 0x0274, 0, 0), 1132 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001, 1133 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), 1134 PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001, 1135 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), 1136 }; 1137 1138 static int clk_mt8183_apmixed_probe(struct platform_device *pdev) 1139 { 1140 struct clk_onecell_data *clk_data; 1141 struct device_node *node = pdev->dev.of_node; 1142 1143 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1144 1145 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1146 1147 mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), 1148 clk_data); 1149 1150 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1151 } 1152 1153 static struct clk_onecell_data *top_clk_data; 1154 1155 static void clk_mt8183_top_init_early(struct device_node *node) 1156 { 1157 int i; 1158 1159 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1160 1161 for (i = 0; i < CLK_TOP_NR_CLK; i++) 1162 top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); 1163 1164 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1165 top_clk_data); 1166 1167 of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); 1168 } 1169 1170 CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", 1171 clk_mt8183_top_init_early); 1172 1173 static int clk_mt8183_top_probe(struct platform_device *pdev) 1174 { 1175 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1176 void __iomem *base; 1177 struct device_node *node = pdev->dev.of_node; 1178 1179 base = devm_ioremap_resource(&pdev->dev, res); 1180 if (IS_ERR(base)) 1181 return PTR_ERR(base); 1182 1183 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 1184 top_clk_data); 1185 1186 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1187 top_clk_data); 1188 1189 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); 1190 1191 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), 1192 node, &mt8183_clk_lock, top_clk_data); 1193 1194 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), 1195 base, &mt8183_clk_lock, top_clk_data); 1196 1197 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), 1198 base, &mt8183_clk_lock, top_clk_data); 1199 1200 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 1201 top_clk_data); 1202 1203 return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); 1204 } 1205 1206 static int clk_mt8183_infra_probe(struct platform_device *pdev) 1207 { 1208 struct clk_onecell_data *clk_data; 1209 struct device_node *node = pdev->dev.of_node; 1210 1211 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1212 1213 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1214 clk_data); 1215 1216 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1217 } 1218 1219 static int clk_mt8183_mcu_probe(struct platform_device *pdev) 1220 { 1221 struct clk_onecell_data *clk_data; 1222 struct device_node *node = pdev->dev.of_node; 1223 void __iomem *base; 1224 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1225 1226 base = devm_ioremap_resource(&pdev->dev, res); 1227 if (IS_ERR(base)) 1228 return PTR_ERR(base); 1229 1230 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); 1231 1232 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, 1233 &mt8183_clk_lock, clk_data); 1234 1235 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1236 } 1237 1238 static const struct of_device_id of_match_clk_mt8183[] = { 1239 { 1240 .compatible = "mediatek,mt8183-apmixedsys", 1241 .data = clk_mt8183_apmixed_probe, 1242 }, { 1243 .compatible = "mediatek,mt8183-topckgen", 1244 .data = clk_mt8183_top_probe, 1245 }, { 1246 .compatible = "mediatek,mt8183-infracfg", 1247 .data = clk_mt8183_infra_probe, 1248 }, { 1249 .compatible = "mediatek,mt8183-mcucfg", 1250 .data = clk_mt8183_mcu_probe, 1251 }, { 1252 /* sentinel */ 1253 } 1254 }; 1255 1256 static int clk_mt8183_probe(struct platform_device *pdev) 1257 { 1258 int (*clk_probe)(struct platform_device *pdev); 1259 int r; 1260 1261 clk_probe = of_device_get_match_data(&pdev->dev); 1262 if (!clk_probe) 1263 return -EINVAL; 1264 1265 r = clk_probe(pdev); 1266 if (r) 1267 dev_err(&pdev->dev, 1268 "could not register clock provider: %s: %d\n", 1269 pdev->name, r); 1270 1271 return r; 1272 } 1273 1274 static struct platform_driver clk_mt8183_drv = { 1275 .probe = clk_mt8183_probe, 1276 .driver = { 1277 .name = "clk-mt8183", 1278 .of_match_table = of_match_clk_mt8183, 1279 }, 1280 }; 1281 1282 static int __init clk_mt8183_init(void) 1283 { 1284 return platform_driver_register(&clk_mt8183_drv); 1285 } 1286 1287 arch_initcall(clk_mt8183_init); 1288