1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 6 #include <linux/delay.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 14 #include "clk-mtk.h" 15 #include "clk-mux.h" 16 #include "clk-gate.h" 17 18 #include <dt-bindings/clock/mt8183-clk.h> 19 20 static DEFINE_SPINLOCK(mt8183_clk_lock); 21 22 static const struct mtk_fixed_clk top_fixed_clks[] = { 23 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 24 FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 25 FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 26 }; 27 28 static const struct mtk_fixed_factor top_divs[] = { 29 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 30 2), 31 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 32 2), 33 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 34 1), 35 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 36 2), 37 FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 38 2), 39 FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 40 4), 41 FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 42 8), 43 FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 44 16), 45 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 46 3), 47 FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 48 2), 49 FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 50 4), 51 FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 52 8), 53 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 54 5), 55 FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 56 2), 57 FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 58 4), 59 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 60 7), 61 FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 62 2), 63 FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 64 4), 65 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 66 1), 67 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 68 2), 69 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 70 2), 71 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 72 4), 73 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 74 8), 75 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 76 3), 77 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 78 2), 79 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 80 4), 81 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 82 8), 83 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 84 5), 85 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 86 2), 87 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 88 4), 89 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 90 8), 91 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 92 7), 93 FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 94 1), 95 FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 96 2), 97 FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 98 4), 99 FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 100 8), 101 FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 102 16), 103 FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 104 32), 105 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 106 1), 107 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 108 2), 109 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 110 4), 111 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 112 8), 113 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 114 1), 115 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 116 2), 117 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 118 4), 119 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 120 8), 121 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 122 1), 123 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 124 2), 125 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 126 4), 127 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 128 8), 129 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 130 16), 131 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 132 1), 133 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 134 4), 135 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 136 2), 137 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 138 4), 139 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 140 5), 141 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 142 2), 143 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 144 4), 145 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 146 6), 147 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 148 7), 149 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 150 1), 151 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 152 1), 153 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 154 2), 155 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 156 4), 157 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 158 8), 159 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 160 16), 161 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 162 1), 163 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 164 2), 165 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 166 4), 167 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 168 8), 169 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 170 16), 171 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 172 2), 173 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 174 16), 175 }; 176 177 static const char * const axi_parents[] = { 178 "clk26m", 179 "syspll_d2_d4", 180 "syspll_d7", 181 "osc_d4" 182 }; 183 184 static const char * const mm_parents[] = { 185 "clk26m", 186 "mmpll_d7", 187 "syspll_d3", 188 "univpll_d2_d2", 189 "syspll_d2_d2", 190 "syspll_d3_d2" 191 }; 192 193 static const char * const img_parents[] = { 194 "clk26m", 195 "mmpll_d6", 196 "univpll_d3", 197 "syspll_d3", 198 "univpll_d2_d2", 199 "syspll_d2_d2", 200 "univpll_d3_d2", 201 "syspll_d3_d2" 202 }; 203 204 static const char * const cam_parents[] = { 205 "clk26m", 206 "syspll_d2", 207 "mmpll_d6", 208 "syspll_d3", 209 "mmpll_d7", 210 "univpll_d3", 211 "univpll_d2_d2", 212 "syspll_d2_d2", 213 "syspll_d3_d2", 214 "univpll_d3_d2" 215 }; 216 217 static const char * const dsp_parents[] = { 218 "clk26m", 219 "mmpll_d6", 220 "mmpll_d7", 221 "univpll_d3", 222 "syspll_d3", 223 "univpll_d2_d2", 224 "syspll_d2_d2", 225 "univpll_d3_d2", 226 "syspll_d3_d2" 227 }; 228 229 static const char * const dsp1_parents[] = { 230 "clk26m", 231 "mmpll_d6", 232 "mmpll_d7", 233 "univpll_d3", 234 "syspll_d3", 235 "univpll_d2_d2", 236 "syspll_d2_d2", 237 "univpll_d3_d2", 238 "syspll_d3_d2" 239 }; 240 241 static const char * const dsp2_parents[] = { 242 "clk26m", 243 "mmpll_d6", 244 "mmpll_d7", 245 "univpll_d3", 246 "syspll_d3", 247 "univpll_d2_d2", 248 "syspll_d2_d2", 249 "univpll_d3_d2", 250 "syspll_d3_d2" 251 }; 252 253 static const char * const ipu_if_parents[] = { 254 "clk26m", 255 "mmpll_d6", 256 "mmpll_d7", 257 "univpll_d3", 258 "syspll_d3", 259 "univpll_d2_d2", 260 "syspll_d2_d2", 261 "univpll_d3_d2", 262 "syspll_d3_d2" 263 }; 264 265 static const char * const mfg_parents[] = { 266 "clk26m", 267 "mfgpll_ck", 268 "univpll_d3", 269 "syspll_d3" 270 }; 271 272 static const char * const f52m_mfg_parents[] = { 273 "clk26m", 274 "univpll_d3_d2", 275 "univpll_d3_d4", 276 "univpll_d3_d8" 277 }; 278 279 static const char * const camtg_parents[] = { 280 "clk26m", 281 "univ_192m_d8", 282 "univpll_d3_d8", 283 "univ_192m_d4", 284 "univpll_d3_d16", 285 "csw_f26m_ck_d2", 286 "univ_192m_d16", 287 "univ_192m_d32" 288 }; 289 290 static const char * const camtg2_parents[] = { 291 "clk26m", 292 "univ_192m_d8", 293 "univpll_d3_d8", 294 "univ_192m_d4", 295 "univpll_d3_d16", 296 "csw_f26m_ck_d2", 297 "univ_192m_d16", 298 "univ_192m_d32" 299 }; 300 301 static const char * const camtg3_parents[] = { 302 "clk26m", 303 "univ_192m_d8", 304 "univpll_d3_d8", 305 "univ_192m_d4", 306 "univpll_d3_d16", 307 "csw_f26m_ck_d2", 308 "univ_192m_d16", 309 "univ_192m_d32" 310 }; 311 312 static const char * const camtg4_parents[] = { 313 "clk26m", 314 "univ_192m_d8", 315 "univpll_d3_d8", 316 "univ_192m_d4", 317 "univpll_d3_d16", 318 "csw_f26m_ck_d2", 319 "univ_192m_d16", 320 "univ_192m_d32" 321 }; 322 323 static const char * const uart_parents[] = { 324 "clk26m", 325 "univpll_d3_d8" 326 }; 327 328 static const char * const spi_parents[] = { 329 "clk26m", 330 "syspll_d5_d2", 331 "syspll_d3_d4", 332 "msdcpll_d4" 333 }; 334 335 static const char * const msdc50_hclk_parents[] = { 336 "clk26m", 337 "syspll_d2_d2", 338 "syspll_d3_d2" 339 }; 340 341 static const char * const msdc50_0_parents[] = { 342 "clk26m", 343 "msdcpll_ck", 344 "msdcpll_d2", 345 "univpll_d2_d4", 346 "syspll_d3_d2", 347 "univpll_d2_d2" 348 }; 349 350 static const char * const msdc30_1_parents[] = { 351 "clk26m", 352 "univpll_d3_d2", 353 "syspll_d3_d2", 354 "syspll_d7", 355 "msdcpll_d2" 356 }; 357 358 static const char * const msdc30_2_parents[] = { 359 "clk26m", 360 "univpll_d3_d2", 361 "syspll_d3_d2", 362 "syspll_d7", 363 "msdcpll_d2" 364 }; 365 366 static const char * const audio_parents[] = { 367 "clk26m", 368 "syspll_d5_d4", 369 "syspll_d7_d4", 370 "syspll_d2_d16" 371 }; 372 373 static const char * const aud_intbus_parents[] = { 374 "clk26m", 375 "syspll_d2_d4", 376 "syspll_d7_d2" 377 }; 378 379 static const char * const pmicspi_parents[] = { 380 "clk26m", 381 "syspll_d2_d8", 382 "osc_d8" 383 }; 384 385 static const char * const fpwrap_ulposc_parents[] = { 386 "clk26m", 387 "osc_d16", 388 "osc_d4", 389 "osc_d8" 390 }; 391 392 static const char * const atb_parents[] = { 393 "clk26m", 394 "syspll_d2_d2", 395 "syspll_d5" 396 }; 397 398 static const char * const sspm_parents[] = { 399 "clk26m", 400 "univpll_d2_d4", 401 "syspll_d2_d2", 402 "univpll_d2_d2", 403 "syspll_d3" 404 }; 405 406 static const char * const dpi0_parents[] = { 407 "clk26m", 408 "tvdpll_d2", 409 "tvdpll_d4", 410 "tvdpll_d8", 411 "tvdpll_d16", 412 "univpll_d5_d2", 413 "univpll_d3_d4", 414 "syspll_d3_d4", 415 "univpll_d3_d8" 416 }; 417 418 static const char * const scam_parents[] = { 419 "clk26m", 420 "syspll_d5_d2" 421 }; 422 423 static const char * const disppwm_parents[] = { 424 "clk26m", 425 "univpll_d3_d4", 426 "osc_d2", 427 "osc_d4", 428 "osc_d16" 429 }; 430 431 static const char * const usb_top_parents[] = { 432 "clk26m", 433 "univpll_d5_d4", 434 "univpll_d3_d4", 435 "univpll_d5_d2" 436 }; 437 438 439 static const char * const ssusb_top_xhci_parents[] = { 440 "clk26m", 441 "univpll_d5_d4", 442 "univpll_d3_d4", 443 "univpll_d5_d2" 444 }; 445 446 static const char * const spm_parents[] = { 447 "clk26m", 448 "syspll_d2_d8" 449 }; 450 451 static const char * const i2c_parents[] = { 452 "clk26m", 453 "syspll_d2_d8", 454 "univpll_d5_d2" 455 }; 456 457 static const char * const scp_parents[] = { 458 "clk26m", 459 "univpll_d2_d8", 460 "syspll_d5", 461 "syspll_d2_d2", 462 "univpll_d2_d2", 463 "syspll_d3", 464 "univpll_d3" 465 }; 466 467 static const char * const seninf_parents[] = { 468 "clk26m", 469 "univpll_d2_d2", 470 "univpll_d3_d2", 471 "univpll_d2_d4" 472 }; 473 474 static const char * const dxcc_parents[] = { 475 "clk26m", 476 "syspll_d2_d2", 477 "syspll_d2_d4", 478 "syspll_d2_d8" 479 }; 480 481 static const char * const aud_engen1_parents[] = { 482 "clk26m", 483 "apll1_d2", 484 "apll1_d4", 485 "apll1_d8" 486 }; 487 488 static const char * const aud_engen2_parents[] = { 489 "clk26m", 490 "apll2_d2", 491 "apll2_d4", 492 "apll2_d8" 493 }; 494 495 static const char * const faes_ufsfde_parents[] = { 496 "clk26m", 497 "syspll_d2", 498 "syspll_d2_d2", 499 "syspll_d3", 500 "syspll_d2_d4", 501 "univpll_d3" 502 }; 503 504 static const char * const fufs_parents[] = { 505 "clk26m", 506 "syspll_d2_d4", 507 "syspll_d2_d8", 508 "syspll_d2_d16" 509 }; 510 511 static const char * const aud_1_parents[] = { 512 "clk26m", 513 "apll1_ck" 514 }; 515 516 static const char * const aud_2_parents[] = { 517 "clk26m", 518 "apll2_ck" 519 }; 520 521 /* 522 * CRITICAL CLOCK: 523 * axi_sel is the main bus clock of whole SOC. 524 * spm_sel is the clock of the always-on co-processor. 525 */ 526 static const struct mtk_mux top_muxes[] = { 527 /* CLK_CFG_0 */ 528 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 529 axi_parents, 0x40, 530 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), 531 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 532 mm_parents, 0x40, 533 0x44, 0x48, 8, 3, 15, 0x004, 1), 534 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 535 img_parents, 0x40, 536 0x44, 0x48, 16, 3, 23, 0x004, 2), 537 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 538 cam_parents, 0x40, 539 0x44, 0x48, 24, 4, 31, 0x004, 3), 540 /* CLK_CFG_1 */ 541 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 542 dsp_parents, 0x50, 543 0x54, 0x58, 0, 4, 7, 0x004, 4), 544 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 545 dsp1_parents, 0x50, 546 0x54, 0x58, 8, 4, 15, 0x004, 5), 547 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 548 dsp2_parents, 0x50, 549 0x54, 0x58, 16, 4, 23, 0x004, 6), 550 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 551 ipu_if_parents, 0x50, 552 0x54, 0x58, 24, 4, 31, 0x004, 7), 553 /* CLK_CFG_2 */ 554 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 555 mfg_parents, 0x60, 556 0x64, 0x68, 0, 2, 7, 0x004, 8), 557 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 558 f52m_mfg_parents, 0x60, 559 0x64, 0x68, 8, 2, 15, 0x004, 9), 560 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 561 camtg_parents, 0x60, 562 0x64, 0x68, 16, 3, 23, 0x004, 10), 563 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 564 camtg2_parents, 0x60, 565 0x64, 0x68, 24, 3, 31, 0x004, 11), 566 /* CLK_CFG_3 */ 567 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 568 camtg3_parents, 0x70, 569 0x74, 0x78, 0, 3, 7, 0x004, 12), 570 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 571 camtg4_parents, 0x70, 572 0x74, 0x78, 8, 3, 15, 0x004, 13), 573 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 574 uart_parents, 0x70, 575 0x74, 0x78, 16, 1, 23, 0x004, 14), 576 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 577 spi_parents, 0x70, 578 0x74, 0x78, 24, 2, 31, 0x004, 15), 579 /* CLK_CFG_4 */ 580 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 581 msdc50_hclk_parents, 0x80, 582 0x84, 0x88, 0, 2, 7, 0x004, 16), 583 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 584 msdc50_0_parents, 0x80, 585 0x84, 0x88, 8, 3, 15, 0x004, 17), 586 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 587 msdc30_1_parents, 0x80, 588 0x84, 0x88, 16, 3, 23, 0x004, 18), 589 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 590 msdc30_2_parents, 0x80, 591 0x84, 0x88, 24, 3, 31, 0x004, 19), 592 /* CLK_CFG_5 */ 593 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 594 audio_parents, 0x90, 595 0x94, 0x98, 0, 2, 7, 0x004, 20), 596 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 597 aud_intbus_parents, 0x90, 598 0x94, 0x98, 8, 2, 15, 0x004, 21), 599 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 600 pmicspi_parents, 0x90, 601 0x94, 0x98, 16, 2, 23, 0x004, 22), 602 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 603 fpwrap_ulposc_parents, 0x90, 604 0x94, 0x98, 24, 2, 31, 0x004, 23), 605 /* CLK_CFG_6 */ 606 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 607 atb_parents, 0xa0, 608 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 609 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSPM, "sspm_sel", 610 sspm_parents, 0xa0, 611 0xa4, 0xa8, 8, 3, 15, 0x004, 25), 612 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 613 dpi0_parents, 0xa0, 614 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 615 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 616 scam_parents, 0xa0, 617 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 618 /* CLK_CFG_7 */ 619 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 620 disppwm_parents, 0xb0, 621 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 622 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 623 usb_top_parents, 0xb0, 624 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 625 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 626 ssusb_top_xhci_parents, 0xb0, 627 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 628 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 629 spm_parents, 0xb0, 630 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), 631 /* CLK_CFG_8 */ 632 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 633 i2c_parents, 0xc0, 634 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 635 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 636 scp_parents, 0xc0, 637 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 638 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 639 seninf_parents, 0xc0, 640 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 641 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 642 dxcc_parents, 0xc0, 643 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 644 /* CLK_CFG_9 */ 645 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 646 aud_engen1_parents, 0xd0, 647 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 648 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 649 aud_engen2_parents, 0xd0, 650 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 651 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 652 faes_ufsfde_parents, 0xd0, 653 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 654 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 655 fufs_parents, 0xd0, 656 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 657 /* CLK_CFG_10 */ 658 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 659 aud_1_parents, 0xe0, 660 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 661 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 662 aud_2_parents, 0xe0, 663 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 664 }; 665 666 static const char * const apll_i2s0_parents[] = { 667 "aud_1_sel", 668 "aud_2_sel" 669 }; 670 671 static const char * const apll_i2s1_parents[] = { 672 "aud_1_sel", 673 "aud_2_sel" 674 }; 675 676 static const char * const apll_i2s2_parents[] = { 677 "aud_1_sel", 678 "aud_2_sel" 679 }; 680 681 static const char * const apll_i2s3_parents[] = { 682 "aud_1_sel", 683 "aud_2_sel" 684 }; 685 686 static const char * const apll_i2s4_parents[] = { 687 "aud_1_sel", 688 "aud_2_sel" 689 }; 690 691 static const char * const apll_i2s5_parents[] = { 692 "aud_1_sel", 693 "aud_2_sel" 694 }; 695 696 static struct mtk_composite top_aud_muxes[] = { 697 MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 698 0x320, 8, 1), 699 MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 700 0x320, 9, 1), 701 MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 702 0x320, 10, 1), 703 MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 704 0x320, 11, 1), 705 MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 706 0x320, 12, 1), 707 MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 708 0x328, 20, 1), 709 }; 710 711 static const char * const mcu_mp0_parents[] = { 712 "clk26m", 713 "armpll_ll", 714 "armpll_div_pll1", 715 "armpll_div_pll2" 716 }; 717 718 static const char * const mcu_mp2_parents[] = { 719 "clk26m", 720 "armpll_l", 721 "armpll_div_pll1", 722 "armpll_div_pll2" 723 }; 724 725 static const char * const mcu_bus_parents[] = { 726 "clk26m", 727 "ccipll", 728 "armpll_div_pll1", 729 "armpll_div_pll2" 730 }; 731 732 static struct mtk_composite mcu_muxes[] = { 733 /* mp0_pll_divider_cfg */ 734 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 735 /* mp2_pll_divider_cfg */ 736 MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 737 /* bus_pll_divider_cfg */ 738 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 739 }; 740 741 static struct mtk_composite top_aud_divs[] = { 742 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 743 0x320, 2, 0x324, 8, 0), 744 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 745 0x320, 3, 0x324, 8, 8), 746 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 747 0x320, 4, 0x324, 8, 16), 748 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 749 0x320, 5, 0x324, 8, 24), 750 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 751 0x320, 6, 0x328, 8, 0), 752 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 753 0x320, 7, 0x328, 8, 8), 754 }; 755 756 static const struct mtk_gate_regs top_cg_regs = { 757 .set_ofs = 0x104, 758 .clr_ofs = 0x104, 759 .sta_ofs = 0x104, 760 }; 761 762 #define GATE_TOP(_id, _name, _parent, _shift) \ 763 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 764 &mtk_clk_gate_ops_no_setclr_inv) 765 766 static const struct mtk_gate top_clks[] = { 767 /* TOP */ 768 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 769 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 770 }; 771 772 static const struct mtk_gate_regs infra0_cg_regs = { 773 .set_ofs = 0x80, 774 .clr_ofs = 0x84, 775 .sta_ofs = 0x90, 776 }; 777 778 static const struct mtk_gate_regs infra1_cg_regs = { 779 .set_ofs = 0x88, 780 .clr_ofs = 0x8c, 781 .sta_ofs = 0x94, 782 }; 783 784 static const struct mtk_gate_regs infra2_cg_regs = { 785 .set_ofs = 0xa4, 786 .clr_ofs = 0xa8, 787 .sta_ofs = 0xac, 788 }; 789 790 static const struct mtk_gate_regs infra3_cg_regs = { 791 .set_ofs = 0xc0, 792 .clr_ofs = 0xc4, 793 .sta_ofs = 0xc8, 794 }; 795 796 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 797 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 798 &mtk_clk_gate_ops_setclr) 799 800 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 801 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 802 &mtk_clk_gate_ops_setclr) 803 804 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 805 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 806 &mtk_clk_gate_ops_setclr) 807 808 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 809 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 810 &mtk_clk_gate_ops_setclr) 811 812 static const struct mtk_gate infra_clks[] = { 813 /* INFRA0 */ 814 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 815 "axi_sel", 0), 816 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 817 "axi_sel", 1), 818 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 819 "axi_sel", 2), 820 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", 821 "axi_sel", 3), 822 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", 823 "scp_sel", 4), 824 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", 825 "f_f26m_ck", 5), 826 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", 827 "axi_sel", 6), 828 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", 829 "axi_sel", 8), 830 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", 831 "axi_sel", 9), 832 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", 833 "axi_sel", 10), 834 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", 835 "i2c_sel", 11), 836 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", 837 "i2c_sel", 12), 838 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", 839 "i2c_sel", 13), 840 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", 841 "i2c_sel", 14), 842 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", 843 "axi_sel", 15), 844 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", 845 "i2c_sel", 16), 846 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", 847 "i2c_sel", 17), 848 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", 849 "i2c_sel", 18), 850 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", 851 "i2c_sel", 19), 852 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 853 "i2c_sel", 21), 854 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 855 "uart_sel", 22), 856 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 857 "uart_sel", 23), 858 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", 859 "uart_sel", 24), 860 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", 861 "uart_sel", 25), 862 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", 863 "axi_sel", 27), 864 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", 865 "axi_sel", 28), 866 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", 867 "axi_sel", 31), 868 /* INFRA1 */ 869 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", 870 "spi_sel", 1), 871 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", 872 "msdc50_hclk_sel", 2), 873 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", 874 "axi_sel", 4), 875 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", 876 "axi_sel", 5), 877 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", 878 "msdc50_0_sel", 6), 879 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", 880 "f_f26m_ck", 7), 881 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", 882 "axi_sel", 8), 883 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", 884 "axi_sel", 9), 885 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", 886 "f_f26m_ck", 10), 887 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", 888 "axi_sel", 11), 889 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", 890 "axi_sel", 12), 891 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", 892 "axi_sel", 13), 893 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", 894 "f_f26m_ck", 14), 895 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", 896 "msdc30_1_sel", 16), 897 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", 898 "msdc30_2_sel", 17), 899 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", 900 "axi_sel", 18), 901 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", 902 "axi_sel", 19), 903 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", 904 "axi_sel", 20), 905 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", 906 "axi_sel", 23), 907 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", 908 "axi_sel", 24), 909 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", 910 "axi_sel", 25), 911 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", 912 "axi_sel", 26), 913 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", 914 "dxcc_sel", 27), 915 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", 916 "dxcc_sel", 28), 917 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", 918 "axi_sel", 30), 919 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 920 "f_f26m_ck", 31), 921 /* INFRA2 */ 922 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", 923 "f_f26m_ck", 0), 924 GATE_INFRA2(CLK_INFRA_USB, "infra_usb", 925 "usb_top_sel", 1), 926 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", 927 "axi_sel", 2), 928 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", 929 "axi_sel", 3), 930 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", 931 "f_f26m_ck", 4), 932 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", 933 "spi_sel", 6), 934 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", 935 "i2c_sel", 7), 936 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", 937 "f_f26m_ck", 8), 938 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", 939 "spi_sel", 9), 940 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", 941 "spi_sel", 10), 942 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", 943 "ssusb_top_xhci_sel", 11), 944 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", 945 "fufs_sel", 12), 946 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", 947 "fufs_sel", 13), 948 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", 949 "axi_sel", 14), 950 GATE_INFRA2(CLK_INFRA_SSPM, "infra_sspm", 951 "sspm_sel", 15), 952 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", 953 "axi_sel", 16), 954 GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk", 955 "axi_sel", 17), 956 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", 957 "i2c_sel", 18), 958 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", 959 "i2c_sel", 19), 960 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", 961 "i2c_sel", 20), 962 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", 963 "i2c_sel", 21), 964 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", 965 "i2c_sel", 22), 966 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", 967 "i2c_sel", 23), 968 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", 969 "i2c_sel", 24), 970 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", 971 "spi_sel", 25), 972 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", 973 "spi_sel", 26), 974 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", 975 "axi_sel", 27), 976 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", 977 "fufs_sel", 28), 978 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", 979 "faes_ufsfde_sel", 29), 980 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", 981 "fufs_sel", 30), 982 /* INFRA3 */ 983 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", 984 "msdc50_0_sel", 0), 985 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", 986 "msdc50_0_sel", 1), 987 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", 988 "msdc50_0_sel", 2), 989 GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self", 990 "f_f26m_ck", 3), 991 GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self", 992 "f_f26m_ck", 4), 993 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", 994 "axi_sel", 5), 995 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", 996 "i2c_sel", 6), 997 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", 998 "msdc50_hclk_sel", 7), 999 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", 1000 "msdc50_hclk_sel", 8), 1001 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", 1002 "axi_sel", 16), 1003 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", 1004 "axi_sel", 17), 1005 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", 1006 "axi_sel", 18), 1007 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", 1008 "axi_sel", 19), 1009 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", 1010 "f_f26m_ck", 20), 1011 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", 1012 "axi_sel", 21), 1013 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", 1014 "i2c_sel", 22), 1015 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", 1016 "i2c_sel", 23), 1017 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", 1018 "msdc50_0_sel", 24), 1019 }; 1020 1021 static const struct mtk_gate_regs apmixed_cg_regs = { 1022 .set_ofs = 0x20, 1023 .clr_ofs = 0x20, 1024 .sta_ofs = 0x20, 1025 }; 1026 1027 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ 1028 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ 1029 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) 1030 1031 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 1032 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) 1033 1034 /* 1035 * CRITICAL CLOCK: 1036 * apmixed_appll26m is the toppest clock gate of all PLLs. 1037 */ 1038 static const struct mtk_gate apmixed_clks[] = { 1039 /* AUDIO0 */ 1040 GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", 1041 "f_f26m_ck", 4), 1042 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", 1043 "f_f26m_ck", 5, CLK_IS_CRITICAL), 1044 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", 1045 "f_f26m_ck", 6), 1046 GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", 1047 "f_f26m_ck", 7), 1048 GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", 1049 "f_f26m_ck", 8), 1050 GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", 1051 "f_f26m_ck", 9), 1052 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", 1053 "f_f26m_ck", 11), 1054 GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", 1055 "f_f26m_ck", 13), 1056 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 1057 "f_f26m_ck", 14), 1058 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", 1059 "f_f26m_ck", 16), 1060 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", 1061 "f_f26m_ck", 17), 1062 }; 1063 1064 #define MT8183_PLL_FMAX (3800UL * MHZ) 1065 #define MT8183_PLL_FMIN (1500UL * MHZ) 1066 1067 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1068 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1069 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1070 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1071 _pcw_chg_reg, _div_table) { \ 1072 .id = _id, \ 1073 .name = _name, \ 1074 .reg = _reg, \ 1075 .pwr_reg = _pwr_reg, \ 1076 .en_mask = _en_mask, \ 1077 .flags = _flags, \ 1078 .rst_bar_mask = _rst_bar_mask, \ 1079 .fmax = MT8183_PLL_FMAX, \ 1080 .fmin = MT8183_PLL_FMIN, \ 1081 .pcwbits = _pcwbits, \ 1082 .pcwibits = _pcwibits, \ 1083 .pd_reg = _pd_reg, \ 1084 .pd_shift = _pd_shift, \ 1085 .tuner_reg = _tuner_reg, \ 1086 .tuner_en_reg = _tuner_en_reg, \ 1087 .tuner_en_bit = _tuner_en_bit, \ 1088 .pcw_reg = _pcw_reg, \ 1089 .pcw_shift = _pcw_shift, \ 1090 .pcw_chg_reg = _pcw_chg_reg, \ 1091 .div_table = _div_table, \ 1092 } 1093 1094 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1095 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1096 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1097 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1098 _pcw_chg_reg) \ 1099 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1100 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1101 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1102 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1103 _pcw_chg_reg, NULL) 1104 1105 static const struct mtk_pll_div_table armpll_div_table[] = { 1106 { .div = 0, .freq = MT8183_PLL_FMAX }, 1107 { .div = 1, .freq = 1500 * MHZ }, 1108 { .div = 2, .freq = 750 * MHZ }, 1109 { .div = 3, .freq = 375 * MHZ }, 1110 { .div = 4, .freq = 187500000 }, 1111 { } /* sentinel */ 1112 }; 1113 1114 static const struct mtk_pll_div_table mfgpll_div_table[] = { 1115 { .div = 0, .freq = MT8183_PLL_FMAX }, 1116 { .div = 1, .freq = 1600 * MHZ }, 1117 { .div = 2, .freq = 800 * MHZ }, 1118 { .div = 3, .freq = 400 * MHZ }, 1119 { .div = 4, .freq = 200 * MHZ }, 1120 { } /* sentinel */ 1121 }; 1122 1123 static const struct mtk_pll_data plls[] = { 1124 PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001, 1125 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, 1126 0x0204, 0, 0, armpll_div_table), 1127 PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001, 1128 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, 1129 0x0214, 0, 0, armpll_div_table), 1130 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001, 1131 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, 1132 0x0294, 0, 0), 1133 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001, 1134 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, 1135 0x0224, 0, 0), 1136 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001, 1137 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, 1138 0x0234, 0, 0), 1139 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001, 1140 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, 1141 mfgpll_div_table), 1142 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001, 1143 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), 1144 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001, 1145 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), 1146 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001, 1147 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, 1148 0x0274, 0, 0), 1149 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001, 1150 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), 1151 PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001, 1152 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), 1153 }; 1154 1155 static int clk_mt8183_apmixed_probe(struct platform_device *pdev) 1156 { 1157 struct clk_onecell_data *clk_data; 1158 struct device_node *node = pdev->dev.of_node; 1159 1160 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1161 1162 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1163 1164 mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), 1165 clk_data); 1166 1167 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1168 } 1169 1170 static int clk_mt8183_top_probe(struct platform_device *pdev) 1171 { 1172 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1173 void __iomem *base; 1174 struct clk_onecell_data *clk_data; 1175 struct device_node *node = pdev->dev.of_node; 1176 1177 base = devm_ioremap_resource(&pdev->dev, res); 1178 if (IS_ERR(base)) 1179 return PTR_ERR(base); 1180 1181 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1182 1183 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 1184 clk_data); 1185 1186 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 1187 1188 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), 1189 node, &mt8183_clk_lock, clk_data); 1190 1191 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), 1192 base, &mt8183_clk_lock, clk_data); 1193 1194 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), 1195 base, &mt8183_clk_lock, clk_data); 1196 1197 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 1198 clk_data); 1199 1200 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1201 } 1202 1203 static int clk_mt8183_infra_probe(struct platform_device *pdev) 1204 { 1205 struct clk_onecell_data *clk_data; 1206 struct device_node *node = pdev->dev.of_node; 1207 1208 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1209 1210 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1211 clk_data); 1212 1213 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1214 } 1215 1216 static int clk_mt8183_mcu_probe(struct platform_device *pdev) 1217 { 1218 struct clk_onecell_data *clk_data; 1219 struct device_node *node = pdev->dev.of_node; 1220 void __iomem *base; 1221 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1222 1223 base = devm_ioremap_resource(&pdev->dev, res); 1224 if (IS_ERR(base)) 1225 return PTR_ERR(base); 1226 1227 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); 1228 1229 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, 1230 &mt8183_clk_lock, clk_data); 1231 1232 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1233 } 1234 1235 static const struct of_device_id of_match_clk_mt8183[] = { 1236 { 1237 .compatible = "mediatek,mt8183-apmixedsys", 1238 .data = clk_mt8183_apmixed_probe, 1239 }, { 1240 .compatible = "mediatek,mt8183-topckgen", 1241 .data = clk_mt8183_top_probe, 1242 }, { 1243 .compatible = "mediatek,mt8183-infracfg", 1244 .data = clk_mt8183_infra_probe, 1245 }, { 1246 .compatible = "mediatek,mt8183-mcucfg", 1247 .data = clk_mt8183_mcu_probe, 1248 }, { 1249 /* sentinel */ 1250 } 1251 }; 1252 1253 static int clk_mt8183_probe(struct platform_device *pdev) 1254 { 1255 int (*clk_probe)(struct platform_device *pdev); 1256 int r; 1257 1258 clk_probe = of_device_get_match_data(&pdev->dev); 1259 if (!clk_probe) 1260 return -EINVAL; 1261 1262 r = clk_probe(pdev); 1263 if (r) 1264 dev_err(&pdev->dev, 1265 "could not register clock provider: %s: %d\n", 1266 pdev->name, r); 1267 1268 return r; 1269 } 1270 1271 static struct platform_driver clk_mt8183_drv = { 1272 .probe = clk_mt8183_probe, 1273 .driver = { 1274 .name = "clk-mt8183", 1275 .of_match_table = of_match_clk_mt8183, 1276 }, 1277 }; 1278 1279 static int __init clk_mt8183_init(void) 1280 { 1281 return platform_driver_register(&clk_mt8183_drv); 1282 } 1283 1284 arch_initcall(clk_mt8183_init); 1285