1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 6 #include <linux/delay.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/platform_device.h> 9 #include <linux/slab.h> 10 11 #include "clk-gate.h" 12 #include "clk-mtk.h" 13 #include "clk-mux.h" 14 15 #include <dt-bindings/clock/mt8183-clk.h> 16 17 static DEFINE_SPINLOCK(mt8183_clk_lock); 18 19 static const struct mtk_fixed_clk top_fixed_clks[] = { 20 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 21 FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 22 FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 23 }; 24 25 /* 26 * To retain compatibility with older devicetrees, we keep CLK_TOP_CLK13M 27 * valid, but renamed from "clk13m" (defined as fixed clock in the new 28 * devicetrees) to "clk26m_d2", satisfying the older clock assignments. 29 * This means that on new devicetrees "clk26m_d2" is unused. 30 */ 31 static const struct mtk_fixed_factor top_divs[] = { 32 FACTOR(CLK_TOP_CLK13M, "clk26m_d2", "clk26m", 1, 2), 33 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2), 34 FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0), 35 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0), 36 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0), 37 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0), 38 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0), 39 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0), 40 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0), 41 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0), 42 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0), 43 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0), 44 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0), 45 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0), 46 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 4, 0), 47 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0), 48 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 2, 0), 49 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 4, 0), 50 FACTOR_FLAGS(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1, 0), 51 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2, 0), 52 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0), 53 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0), 54 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8, 0), 55 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0), 56 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0), 57 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0), 58 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0), 59 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0), 60 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0), 61 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0), 62 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0), 63 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0), 64 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 1, 0), 65 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 2, 0), 66 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 4, 0), 67 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 8, 0), 68 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 16, 0), 69 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 32, 0), 70 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1), 71 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 72 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 73 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 74 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1), 75 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 76 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 77 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 78 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1), 79 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 80 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 81 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 82 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 83 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1), 84 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 85 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 86 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4), 87 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 88 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 89 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4), 90 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 91 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 92 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1), 93 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1), 94 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 95 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 96 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 97 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16), 98 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1), 99 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2), 100 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4), 101 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8), 102 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16), 103 FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0), 104 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16, 0), 105 }; 106 107 static const char * const axi_parents[] = { 108 "clk26m", 109 "syspll_d2_d4", 110 "syspll_d7", 111 "osc_d4" 112 }; 113 114 static const char * const mm_parents[] = { 115 "clk26m", 116 "mmpll_d7", 117 "syspll_d3", 118 "univpll_d2_d2", 119 "syspll_d2_d2", 120 "syspll_d3_d2" 121 }; 122 123 static const char * const img_parents[] = { 124 "clk26m", 125 "mmpll_d6", 126 "univpll_d3", 127 "syspll_d3", 128 "univpll_d2_d2", 129 "syspll_d2_d2", 130 "univpll_d3_d2", 131 "syspll_d3_d2" 132 }; 133 134 static const char * const cam_parents[] = { 135 "clk26m", 136 "syspll_d2", 137 "mmpll_d6", 138 "syspll_d3", 139 "mmpll_d7", 140 "univpll_d3", 141 "univpll_d2_d2", 142 "syspll_d2_d2", 143 "syspll_d3_d2", 144 "univpll_d3_d2" 145 }; 146 147 static const char * const dsp_parents[] = { 148 "clk26m", 149 "mmpll_d6", 150 "mmpll_d7", 151 "univpll_d3", 152 "syspll_d3", 153 "univpll_d2_d2", 154 "syspll_d2_d2", 155 "univpll_d3_d2", 156 "syspll_d3_d2" 157 }; 158 159 static const char * const dsp1_parents[] = { 160 "clk26m", 161 "mmpll_d6", 162 "mmpll_d7", 163 "univpll_d3", 164 "syspll_d3", 165 "univpll_d2_d2", 166 "syspll_d2_d2", 167 "univpll_d3_d2", 168 "syspll_d3_d2" 169 }; 170 171 static const char * const dsp2_parents[] = { 172 "clk26m", 173 "mmpll_d6", 174 "mmpll_d7", 175 "univpll_d3", 176 "syspll_d3", 177 "univpll_d2_d2", 178 "syspll_d2_d2", 179 "univpll_d3_d2", 180 "syspll_d3_d2" 181 }; 182 183 static const char * const ipu_if_parents[] = { 184 "clk26m", 185 "mmpll_d6", 186 "mmpll_d7", 187 "univpll_d3", 188 "syspll_d3", 189 "univpll_d2_d2", 190 "syspll_d2_d2", 191 "univpll_d3_d2", 192 "syspll_d3_d2" 193 }; 194 195 static const char * const mfg_parents[] = { 196 "clk26m", 197 "mfgpll_ck", 198 "univpll_d3", 199 "syspll_d3" 200 }; 201 202 static const char * const f52m_mfg_parents[] = { 203 "clk26m", 204 "univpll_d3_d2", 205 "univpll_d3_d4", 206 "univpll_d3_d8" 207 }; 208 209 static const char * const camtg_parents[] = { 210 "clk26m", 211 "univ_192m_d8", 212 "univpll_d3_d8", 213 "univ_192m_d4", 214 "univpll_d3_d16", 215 "csw_f26m_ck_d2", 216 "univ_192m_d16", 217 "univ_192m_d32" 218 }; 219 220 static const char * const camtg2_parents[] = { 221 "clk26m", 222 "univ_192m_d8", 223 "univpll_d3_d8", 224 "univ_192m_d4", 225 "univpll_d3_d16", 226 "csw_f26m_ck_d2", 227 "univ_192m_d16", 228 "univ_192m_d32" 229 }; 230 231 static const char * const camtg3_parents[] = { 232 "clk26m", 233 "univ_192m_d8", 234 "univpll_d3_d8", 235 "univ_192m_d4", 236 "univpll_d3_d16", 237 "csw_f26m_ck_d2", 238 "univ_192m_d16", 239 "univ_192m_d32" 240 }; 241 242 static const char * const camtg4_parents[] = { 243 "clk26m", 244 "univ_192m_d8", 245 "univpll_d3_d8", 246 "univ_192m_d4", 247 "univpll_d3_d16", 248 "csw_f26m_ck_d2", 249 "univ_192m_d16", 250 "univ_192m_d32" 251 }; 252 253 static const char * const uart_parents[] = { 254 "clk26m", 255 "univpll_d3_d8" 256 }; 257 258 static const char * const spi_parents[] = { 259 "clk26m", 260 "syspll_d5_d2", 261 "syspll_d3_d4", 262 "msdcpll_d4" 263 }; 264 265 static const char * const msdc50_hclk_parents[] = { 266 "clk26m", 267 "syspll_d2_d2", 268 "syspll_d3_d2" 269 }; 270 271 static const char * const msdc50_0_parents[] = { 272 "clk26m", 273 "msdcpll_ck", 274 "msdcpll_d2", 275 "univpll_d2_d4", 276 "syspll_d3_d2", 277 "univpll_d2_d2" 278 }; 279 280 static const char * const msdc30_1_parents[] = { 281 "clk26m", 282 "univpll_d3_d2", 283 "syspll_d3_d2", 284 "syspll_d7", 285 "msdcpll_d2" 286 }; 287 288 static const char * const msdc30_2_parents[] = { 289 "clk26m", 290 "univpll_d3_d2", 291 "syspll_d3_d2", 292 "syspll_d7", 293 "msdcpll_d2" 294 }; 295 296 static const char * const audio_parents[] = { 297 "clk26m", 298 "syspll_d5_d4", 299 "syspll_d7_d4", 300 "syspll_d2_d16" 301 }; 302 303 static const char * const aud_intbus_parents[] = { 304 "clk26m", 305 "syspll_d2_d4", 306 "syspll_d7_d2" 307 }; 308 309 static const char * const pmicspi_parents[] = { 310 "clk26m", 311 "syspll_d2_d8", 312 "osc_d8" 313 }; 314 315 static const char * const fpwrap_ulposc_parents[] = { 316 "clk26m", 317 "osc_d16", 318 "osc_d4", 319 "osc_d8" 320 }; 321 322 static const char * const atb_parents[] = { 323 "clk26m", 324 "syspll_d2_d2", 325 "syspll_d5" 326 }; 327 328 static const char * const sspm_parents[] = { 329 "clk26m", 330 "univpll_d2_d4", 331 "syspll_d2_d2", 332 "univpll_d2_d2", 333 "syspll_d3" 334 }; 335 336 static const char * const dpi0_parents[] = { 337 "clk26m", 338 "tvdpll_d2", 339 "tvdpll_d4", 340 "tvdpll_d8", 341 "tvdpll_d16", 342 "univpll_d5_d2", 343 "univpll_d3_d4", 344 "syspll_d3_d4", 345 "univpll_d3_d8" 346 }; 347 348 static const char * const scam_parents[] = { 349 "clk26m", 350 "syspll_d5_d2" 351 }; 352 353 static const char * const disppwm_parents[] = { 354 "clk26m", 355 "univpll_d3_d4", 356 "osc_d2", 357 "osc_d4", 358 "osc_d16" 359 }; 360 361 static const char * const usb_top_parents[] = { 362 "clk26m", 363 "univpll_d5_d4", 364 "univpll_d3_d4", 365 "univpll_d5_d2" 366 }; 367 368 369 static const char * const ssusb_top_xhci_parents[] = { 370 "clk26m", 371 "univpll_d5_d4", 372 "univpll_d3_d4", 373 "univpll_d5_d2" 374 }; 375 376 static const char * const spm_parents[] = { 377 "clk26m", 378 "syspll_d2_d8" 379 }; 380 381 static const char * const i2c_parents[] = { 382 "clk26m", 383 "syspll_d2_d8", 384 "univpll_d5_d2" 385 }; 386 387 static const char * const scp_parents[] = { 388 "clk26m", 389 "univpll_d2_d8", 390 "syspll_d5", 391 "syspll_d2_d2", 392 "univpll_d2_d2", 393 "syspll_d3", 394 "univpll_d3" 395 }; 396 397 static const char * const seninf_parents[] = { 398 "clk26m", 399 "univpll_d2_d2", 400 "univpll_d3_d2", 401 "univpll_d2_d4" 402 }; 403 404 static const char * const dxcc_parents[] = { 405 "clk26m", 406 "syspll_d2_d2", 407 "syspll_d2_d4", 408 "syspll_d2_d8" 409 }; 410 411 static const char * const aud_engen1_parents[] = { 412 "clk26m", 413 "apll1_d2", 414 "apll1_d4", 415 "apll1_d8" 416 }; 417 418 static const char * const aud_engen2_parents[] = { 419 "clk26m", 420 "apll2_d2", 421 "apll2_d4", 422 "apll2_d8" 423 }; 424 425 static const char * const faes_ufsfde_parents[] = { 426 "clk26m", 427 "syspll_d2", 428 "syspll_d2_d2", 429 "syspll_d3", 430 "syspll_d2_d4", 431 "univpll_d3" 432 }; 433 434 static const char * const fufs_parents[] = { 435 "clk26m", 436 "syspll_d2_d4", 437 "syspll_d2_d8", 438 "syspll_d2_d16" 439 }; 440 441 static const char * const aud_1_parents[] = { 442 "clk26m", 443 "apll1_ck" 444 }; 445 446 static const char * const aud_2_parents[] = { 447 "clk26m", 448 "apll2_ck" 449 }; 450 451 /* 452 * CRITICAL CLOCK: 453 * axi_sel is the main bus clock of whole SOC. 454 * spm_sel is the clock of the always-on co-processor. 455 */ 456 static const struct mtk_mux top_muxes[] = { 457 /* CLK_CFG_0 */ 458 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 459 axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0, 460 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 461 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 462 mm_parents, 0x40, 0x44, 0x48, 8, 3, 15, 0x004, 1), 463 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 464 img_parents, 0x40, 0x44, 0x48, 16, 3, 23, 0x004, 2), 465 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 466 cam_parents, 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 3), 467 /* CLK_CFG_1 */ 468 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 469 dsp_parents, 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 4), 470 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 471 dsp1_parents, 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 5), 472 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 473 dsp2_parents, 0x50, 0x54, 0x58, 16, 4, 23, 0x004, 6), 474 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 475 ipu_if_parents, 0x50, 0x54, 0x58, 24, 4, 31, 0x004, 7), 476 /* CLK_CFG_2 */ 477 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 478 mfg_parents, 0x60, 0x64, 0x68, 0, 2, 7, 0x004, 8), 479 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 480 f52m_mfg_parents, 0x60, 0x64, 0x68, 8, 2, 15, 0x004, 9), 481 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 482 camtg_parents, 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 10), 483 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 484 camtg2_parents, 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 11), 485 /* CLK_CFG_3 */ 486 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 487 camtg3_parents, 0x70, 0x74, 0x78, 0, 3, 7, 0x004, 12), 488 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 489 camtg4_parents, 0x70, 0x74, 0x78, 8, 3, 15, 0x004, 13), 490 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 491 uart_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x004, 14), 492 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 493 spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15), 494 /* CLK_CFG_4 */ 495 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 496 msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16, 0), 497 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 498 msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17, 0), 499 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 500 msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18, 0), 501 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 502 msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19, 0), 503 /* CLK_CFG_5 */ 504 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 505 audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20), 506 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 507 aud_intbus_parents, 0x90, 0x94, 0x98, 8, 2, 15, 0x004, 21), 508 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 509 pmicspi_parents, 0x90, 0x94, 0x98, 16, 2, 23, 0x004, 22), 510 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 511 fpwrap_ulposc_parents, 0x90, 0x94, 0x98, 24, 2, 31, 0x004, 23), 512 /* CLK_CFG_6 */ 513 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 514 atb_parents, 0xa0, 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 515 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SSPM, "sspm_sel", 516 sspm_parents, 0xa0, 0xa4, 0xa8, 8, 3, 15, 0x004, 25, 517 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 518 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 519 dpi0_parents, 0xa0, 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 520 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 521 scam_parents, 0xa0, 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 522 /* CLK_CFG_7 */ 523 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 524 disppwm_parents, 0xb0, 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 525 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 526 usb_top_parents, 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 527 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 528 ssusb_top_xhci_parents, 0xb0, 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 529 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 530 spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0, 531 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 532 /* CLK_CFG_8 */ 533 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 534 i2c_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 535 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 536 scp_parents, 0xc0, 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 537 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 538 seninf_parents, 0xc0, 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 539 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 540 dxcc_parents, 0xc0, 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 541 /* CLK_CFG_9 */ 542 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 543 aud_engen1_parents, 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 544 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 545 aud_engen2_parents, 0xd0, 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 546 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 547 faes_ufsfde_parents, 0xd0, 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 548 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 549 fufs_parents, 0xd0, 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 550 /* CLK_CFG_10 */ 551 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 552 aud_1_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 553 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 554 aud_2_parents, 0xe0, 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 555 }; 556 557 static const char * const apll_i2s0_parents[] = { 558 "aud_1_sel", 559 "aud_2_sel" 560 }; 561 562 static const char * const apll_i2s1_parents[] = { 563 "aud_1_sel", 564 "aud_2_sel" 565 }; 566 567 static const char * const apll_i2s2_parents[] = { 568 "aud_1_sel", 569 "aud_2_sel" 570 }; 571 572 static const char * const apll_i2s3_parents[] = { 573 "aud_1_sel", 574 "aud_2_sel" 575 }; 576 577 static const char * const apll_i2s4_parents[] = { 578 "aud_1_sel", 579 "aud_2_sel" 580 }; 581 582 static const char * const apll_i2s5_parents[] = { 583 "aud_1_sel", 584 "aud_2_sel" 585 }; 586 587 static const char * const mcu_mp0_parents[] = { 588 "clk26m", 589 "armpll_ll", 590 "armpll_div_pll1", 591 "armpll_div_pll2" 592 }; 593 594 static const char * const mcu_mp2_parents[] = { 595 "clk26m", 596 "armpll_l", 597 "armpll_div_pll1", 598 "armpll_div_pll2" 599 }; 600 601 static const char * const mcu_bus_parents[] = { 602 "clk26m", 603 "ccipll", 604 "armpll_div_pll1", 605 "armpll_div_pll2" 606 }; 607 608 static struct mtk_composite mcu_muxes[] = { 609 /* mp0_pll_divider_cfg */ 610 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 611 /* mp2_pll_divider_cfg */ 612 MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 613 /* bus_pll_divider_cfg */ 614 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 615 }; 616 617 static struct mtk_composite top_aud_comp[] = { 618 MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 0x320, 8, 1), 619 MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 0x320, 9, 1), 620 MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 0x320, 10, 1), 621 MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 0x320, 11, 1), 622 MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 0x320, 12, 1), 623 MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 0x328, 20, 1), 624 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 0x320, 2, 0x324, 8, 0), 625 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 0x320, 3, 0x324, 8, 8), 626 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 0x320, 4, 0x324, 8, 16), 627 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 0x320, 5, 0x324, 8, 24), 628 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 0x320, 6, 0x328, 8, 0), 629 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 7, 0x328, 8, 8), 630 }; 631 632 static const struct mtk_gate_regs top_cg_regs = { 633 .set_ofs = 0x104, 634 .clr_ofs = 0x104, 635 .sta_ofs = 0x104, 636 }; 637 638 #define GATE_TOP(_id, _name, _parent, _shift) \ 639 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 640 &mtk_clk_gate_ops_no_setclr_inv) 641 642 static const struct mtk_gate top_clks[] = { 643 /* TOP */ 644 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 645 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 646 }; 647 648 static const struct mtk_gate_regs infra0_cg_regs = { 649 .set_ofs = 0x80, 650 .clr_ofs = 0x84, 651 .sta_ofs = 0x90, 652 }; 653 654 static const struct mtk_gate_regs infra1_cg_regs = { 655 .set_ofs = 0x88, 656 .clr_ofs = 0x8c, 657 .sta_ofs = 0x94, 658 }; 659 660 static const struct mtk_gate_regs infra2_cg_regs = { 661 .set_ofs = 0xa4, 662 .clr_ofs = 0xa8, 663 .sta_ofs = 0xac, 664 }; 665 666 static const struct mtk_gate_regs infra3_cg_regs = { 667 .set_ofs = 0xc0, 668 .clr_ofs = 0xc4, 669 .sta_ofs = 0xc8, 670 }; 671 672 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 673 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 674 &mtk_clk_gate_ops_setclr) 675 676 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 677 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 678 &mtk_clk_gate_ops_setclr) 679 680 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 681 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 682 &mtk_clk_gate_ops_setclr) 683 684 #define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flag) \ 685 GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, \ 686 _shift, &mtk_clk_gate_ops_setclr, _flag) 687 688 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 689 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 690 &mtk_clk_gate_ops_setclr) 691 692 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \ 693 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, \ 694 _shift, &mtk_clk_gate_ops_setclr, _flag) 695 696 static const struct mtk_gate infra_clks[] = { 697 /* INFRA0 */ 698 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0), 699 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "axi_sel", 1), 700 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "axi_sel", 2), 701 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "axi_sel", 3), 702 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", "scp_sel", 4), 703 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "f_f26m_ck", 5), 704 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 705 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", "axi_sel", 8), 706 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9), 707 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 708 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), 709 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", "i2c_sel", 12), 710 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), 711 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), 712 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15), 713 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "i2c_sel", 16), 714 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "i2c_sel", 17), 715 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "i2c_sel", 18), 716 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "i2c_sel", 19), 717 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "i2c_sel", 21), 718 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 719 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 720 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 721 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 722 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), 723 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", "axi_sel", 28), 724 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 725 /* INFRA1 */ 726 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), 727 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_hclk_sel", 2), 728 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "axi_sel", 4), 729 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "axi_sel", 5), 730 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", "msdc50_0_sel", 6), 731 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", "f_f26m_ck", 7), 732 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 733 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 734 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "f_f26m_ck", 10), 735 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 736 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), 737 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), 738 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "f_f26m_ck", 14), 739 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", "msdc30_1_sel", 16), 740 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", "msdc30_2_sel", 17), 741 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", "axi_sel", 18), 742 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", "axi_sel", 19), 743 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20), 744 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 745 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), 746 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 747 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 748 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), 749 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), 750 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", "axi_sel", 30), 751 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "f_f26m_ck", 31), 752 /* INFRA2 */ 753 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "f_f26m_ck", 0), 754 GATE_INFRA2(CLK_INFRA_USB, "infra_usb", "usb_top_sel", 1), 755 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", "axi_sel", 2), 756 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", "axi_sel", 3), 757 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", "f_f26m_ck", 4), 758 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), 759 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), 760 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", "f_f26m_ck", 8), 761 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), 762 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), 763 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", "ssusb_top_xhci_sel", 11), 764 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "fufs_sel", 12), 765 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", "fufs_sel", 13), 766 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14), 767 /* infra_sspm is main clock in co-processor, should not be closed in Linux. */ 768 GATE_INFRA2_FLAGS(CLK_INFRA_SSPM, "infra_sspm", "sspm_sel", 15, CLK_IS_CRITICAL), 769 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), 770 /* infra_sspm_bus_hclk is main clock in co-processor, should not be closed in Linux. */ 771 GATE_INFRA2_FLAGS(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk", "axi_sel", 17, CLK_IS_CRITICAL), 772 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), 773 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), 774 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), 775 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), 776 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), 777 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), 778 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), 779 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), 780 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), 781 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", "axi_sel", 27), 782 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "fufs_sel", 28), 783 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "faes_ufsfde_sel", 29), 784 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "fufs_sel", 30), 785 /* INFRA3 */ 786 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), 787 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), 788 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), 789 /* infra_sspm_26m_self is main clock in co-processor, should not be closed in Linux. */ 790 GATE_INFRA3_FLAGS(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self", "f_f26m_ck", 3, CLK_IS_CRITICAL), 791 /* infra_sspm_32k_self is main clock in co-processor, should not be closed in Linux. */ 792 GATE_INFRA3_FLAGS(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self", "clk32k", 4, CLK_IS_CRITICAL), 793 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), 794 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), 795 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_hclk_sel", 7), 796 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_hclk_sel", 8), 797 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), 798 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), 799 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), 800 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), 801 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "f_f26m_ck", 20), 802 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", "axi_sel", 21), 803 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), 804 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), 805 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), 806 }; 807 808 static const struct mtk_gate_regs peri_cg_regs = { 809 .set_ofs = 0x20c, 810 .clr_ofs = 0x20c, 811 .sta_ofs = 0x20c, 812 }; 813 814 #define GATE_PERI(_id, _name, _parent, _shift) \ 815 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ 816 &mtk_clk_gate_ops_no_setclr_inv) 817 818 static const struct mtk_gate peri_clks[] = { 819 GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), 820 }; 821 822 static u16 infra_rst_ofs[] = { 823 INFRA_RST0_SET_OFFSET, 824 INFRA_RST1_SET_OFFSET, 825 INFRA_RST2_SET_OFFSET, 826 INFRA_RST3_SET_OFFSET, 827 }; 828 829 static const struct mtk_clk_rst_desc clk_rst_desc = { 830 .version = MTK_RST_SET_CLR, 831 .rst_bank_ofs = infra_rst_ofs, 832 .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), 833 }; 834 835 /* Register mux notifier for MFG mux */ 836 static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) 837 { 838 struct mtk_mux_nb *mfg_mux_nb; 839 int i; 840 841 mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); 842 if (!mfg_mux_nb) 843 return -ENOMEM; 844 845 for (i = 0; i < ARRAY_SIZE(top_muxes); i++) 846 if (top_muxes[i].id == CLK_TOP_MUX_MFG) 847 break; 848 if (i == ARRAY_SIZE(top_muxes)) 849 return -EINVAL; 850 851 mfg_mux_nb->ops = top_muxes[i].ops; 852 mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */ 853 854 return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); 855 } 856 857 static const struct mtk_clk_desc infra_desc = { 858 .clks = infra_clks, 859 .num_clks = ARRAY_SIZE(infra_clks), 860 .rst_desc = &clk_rst_desc, 861 }; 862 863 static const struct mtk_clk_desc mcu_desc = { 864 .composite_clks = mcu_muxes, 865 .num_composite_clks = ARRAY_SIZE(mcu_muxes), 866 .clk_lock = &mt8183_clk_lock, 867 }; 868 869 static const struct mtk_clk_desc peri_desc = { 870 .clks = peri_clks, 871 .num_clks = ARRAY_SIZE(peri_clks), 872 }; 873 874 static const struct mtk_clk_desc topck_desc = { 875 .fixed_clks = top_fixed_clks, 876 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 877 .factor_clks = top_divs, 878 .num_factor_clks = ARRAY_SIZE(top_divs), 879 .mux_clks = top_muxes, 880 .num_mux_clks = ARRAY_SIZE(top_muxes), 881 .composite_clks = top_aud_comp, 882 .num_composite_clks = ARRAY_SIZE(top_aud_comp), 883 .clks = top_clks, 884 .num_clks = ARRAY_SIZE(top_clks), 885 .clk_lock = &mt8183_clk_lock, 886 .clk_notifier_func = clk_mt8183_reg_mfg_mux_notifier, 887 .mfg_clk_idx = CLK_TOP_MUX_MFG, 888 }; 889 890 static const struct of_device_id of_match_clk_mt8183[] = { 891 { .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc }, 892 { .compatible = "mediatek,mt8183-mcucfg", .data = &mcu_desc }, 893 { .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, }, 894 { .compatible = "mediatek,mt8183-topckgen", .data = &topck_desc }, 895 { /* sentinel */ } 896 }; 897 MODULE_DEVICE_TABLE(of, of_match_clk_mt8183); 898 899 static struct platform_driver clk_mt8183_drv = { 900 .probe = mtk_clk_simple_probe, 901 .remove = mtk_clk_simple_remove, 902 .driver = { 903 .name = "clk-mt8183", 904 .of_match_table = of_match_clk_mt8183, 905 }, 906 }; 907 module_platform_driver(clk_mt8183_drv) 908 909 MODULE_DESCRIPTION("MediaTek MT8183 main clocks driver"); 910 MODULE_LICENSE("GPL"); 911