xref: /linux/drivers/clk/mediatek/clk-mt8183-vdec.c (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1acddfc2cSWeiyi Lu // SPDX-License-Identifier: GPL-2.0
2acddfc2cSWeiyi Lu //
3acddfc2cSWeiyi Lu // Copyright (c) 2018 MediaTek Inc.
4acddfc2cSWeiyi Lu // Author: Weiyi Lu <weiyi.lu@mediatek.com>
5acddfc2cSWeiyi Lu 
6acddfc2cSWeiyi Lu #include <linux/clk-provider.h>
7acddfc2cSWeiyi Lu #include <linux/platform_device.h>
8acddfc2cSWeiyi Lu 
9acddfc2cSWeiyi Lu #include "clk-mtk.h"
10acddfc2cSWeiyi Lu #include "clk-gate.h"
11acddfc2cSWeiyi Lu 
12acddfc2cSWeiyi Lu #include <dt-bindings/clock/mt8183-clk.h>
13acddfc2cSWeiyi Lu 
14acddfc2cSWeiyi Lu static const struct mtk_gate_regs vdec0_cg_regs = {
15acddfc2cSWeiyi Lu 	.set_ofs = 0x0,
16acddfc2cSWeiyi Lu 	.clr_ofs = 0x4,
17acddfc2cSWeiyi Lu 	.sta_ofs = 0x0,
18acddfc2cSWeiyi Lu };
19acddfc2cSWeiyi Lu 
20acddfc2cSWeiyi Lu static const struct mtk_gate_regs vdec1_cg_regs = {
21acddfc2cSWeiyi Lu 	.set_ofs = 0x8,
22acddfc2cSWeiyi Lu 	.clr_ofs = 0xc,
23acddfc2cSWeiyi Lu 	.sta_ofs = 0x8,
24acddfc2cSWeiyi Lu };
25acddfc2cSWeiyi Lu 
26acddfc2cSWeiyi Lu #define GATE_VDEC0_I(_id, _name, _parent, _shift)		\
27acddfc2cSWeiyi Lu 	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift,	\
28acddfc2cSWeiyi Lu 		&mtk_clk_gate_ops_setclr_inv)
29acddfc2cSWeiyi Lu 
30acddfc2cSWeiyi Lu #define GATE_VDEC1_I(_id, _name, _parent, _shift)		\
31acddfc2cSWeiyi Lu 	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift,	\
32acddfc2cSWeiyi Lu 		&mtk_clk_gate_ops_setclr_inv)
33acddfc2cSWeiyi Lu 
34acddfc2cSWeiyi Lu static const struct mtk_gate vdec_clks[] = {
35acddfc2cSWeiyi Lu 	/* VDEC0 */
36acddfc2cSWeiyi Lu 	GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0),
37acddfc2cSWeiyi Lu 	/* VDEC1 */
38acddfc2cSWeiyi Lu 	GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
39acddfc2cSWeiyi Lu };
40acddfc2cSWeiyi Lu 
41d36d697aSMiles Chen static const struct mtk_clk_desc vdec_desc = {
42d36d697aSMiles Chen 	.clks = vdec_clks,
43d36d697aSMiles Chen 	.num_clks = ARRAY_SIZE(vdec_clks),
44d36d697aSMiles Chen };
45acddfc2cSWeiyi Lu 
46acddfc2cSWeiyi Lu static const struct of_device_id of_match_clk_mt8183_vdec[] = {
47d36d697aSMiles Chen 	{
48d36d697aSMiles Chen 		.compatible = "mediatek,mt8183-vdecsys",
49d36d697aSMiles Chen 		.data = &vdec_desc,
50d36d697aSMiles Chen 	}, {
51d36d697aSMiles Chen 		/* sentinel */
52d36d697aSMiles Chen 	}
53acddfc2cSWeiyi Lu };
5465c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_vdec);
55acddfc2cSWeiyi Lu 
56acddfc2cSWeiyi Lu static struct platform_driver clk_mt8183_vdec_drv = {
57d36d697aSMiles Chen 	.probe = mtk_clk_simple_probe,
58*f00b45dbSUwe Kleine-König 	.remove = mtk_clk_simple_remove,
59acddfc2cSWeiyi Lu 	.driver = {
60acddfc2cSWeiyi Lu 		.name = "clk-mt8183-vdec",
61acddfc2cSWeiyi Lu 		.of_match_table = of_match_clk_mt8183_vdec,
62acddfc2cSWeiyi Lu 	},
63acddfc2cSWeiyi Lu };
64164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt8183_vdec_drv);
65f5100c41SAngeloGioacchino Del Regno 
66f5100c41SAngeloGioacchino Del Regno MODULE_DESCRIPTION("MediaTek MT8183 Video Decoders clocks driver");
67a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL");
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