1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 6 #include <linux/clk-provider.h> 7 #include <linux/platform_device.h> 8 #include <linux/pm_runtime.h> 9 10 #include "clk-mtk.h" 11 #include "clk-gate.h" 12 13 #include <dt-bindings/clock/mt8183-clk.h> 14 15 static const struct mtk_gate_regs mfg_cg_regs = { 16 .set_ofs = 0x4, 17 .clr_ofs = 0x8, 18 .sta_ofs = 0x0, 19 }; 20 21 #define GATE_MFG(_id, _name, _parent, _shift) \ 22 GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \ 23 &mtk_clk_gate_ops_setclr) 24 25 static const struct mtk_gate mfg_clks[] = { 26 GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0) 27 }; 28 29 static int clk_mt8183_mfg_probe(struct platform_device *pdev) 30 { 31 struct clk_onecell_data *clk_data; 32 struct device_node *node = pdev->dev.of_node; 33 34 pm_runtime_enable(&pdev->dev); 35 36 clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK); 37 38 mtk_clk_register_gates_with_dev(node, mfg_clks, ARRAY_SIZE(mfg_clks), 39 clk_data, &pdev->dev); 40 41 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 42 } 43 44 static const struct of_device_id of_match_clk_mt8183_mfg[] = { 45 { .compatible = "mediatek,mt8183-mfgcfg", }, 46 {} 47 }; 48 49 static struct platform_driver clk_mt8183_mfg_drv = { 50 .probe = clk_mt8183_mfg_probe, 51 .driver = { 52 .name = "clk-mt8183-mfg", 53 .of_match_table = of_match_clk_mt8183_mfg, 54 }, 55 }; 56 57 builtin_platform_driver(clk_mt8183_mfg_drv); 58