1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/platform_device.h> 10 11 #include "clk-gate.h" 12 #include "clk-mtk.h" 13 14 #include <dt-bindings/clock/mt8173-clk.h> 15 16 static const struct mtk_gate_regs mm0_cg_regs = { 17 .set_ofs = 0x0104, 18 .clr_ofs = 0x0108, 19 .sta_ofs = 0x0100, 20 }; 21 22 static const struct mtk_gate_regs mm1_cg_regs = { 23 .set_ofs = 0x0114, 24 .clr_ofs = 0x0118, 25 .sta_ofs = 0x0110, 26 }; 27 28 #define GATE_MM0(_id, _name, _parent, _shift) \ 29 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 30 31 #define GATE_MM1(_id, _name, _parent, _shift) \ 32 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 33 34 static const struct mtk_gate mt8173_mm_clks[] = { 35 GATE_DUMMY(CLK_DUMMY, "mm_dummy"), 36 /* MM0 */ 37 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), 38 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), 39 GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2), 40 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3), 41 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4), 42 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5), 43 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6), 44 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7), 45 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8), 46 GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9), 47 GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11), 48 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12), 49 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13), 50 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14), 51 GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15), 52 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16), 53 GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17), 54 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18), 55 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19), 56 GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20), 57 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21), 58 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22), 59 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23), 60 GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24), 61 GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25), 62 GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26), 63 GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27), 64 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28), 65 GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29), 66 GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30), 67 GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31), 68 /* MM1 */ 69 GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0), 70 GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1), 71 GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2), 72 GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3), 73 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4), 74 GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5), 75 GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6), 76 GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7), 77 GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8), 78 GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9), 79 GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10), 80 GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11), 81 GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12), 82 GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13), 83 GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14), 84 GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15), 85 GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16), 86 GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17), 87 GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18), 88 GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19), 89 GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20), 90 }; 91 92 static const struct mtk_clk_desc mm_desc = { 93 .clks = mt8173_mm_clks, 94 .num_clks = ARRAY_SIZE(mt8173_mm_clks), 95 }; 96 97 static const struct platform_device_id clk_mt8173_mm_id_table[] = { 98 { .name = "clk-mt8173-mm", .driver_data = (kernel_ulong_t)&mm_desc }, 99 { /* sentinel */ } 100 }; 101 MODULE_DEVICE_TABLE(platform, clk_mt8173_mm_id_table); 102 103 static struct platform_driver clk_mt8173_mm_drv = { 104 .driver = { 105 .name = "clk-mt8173-mm", 106 }, 107 .id_table = clk_mt8173_mm_id_table, 108 .probe = mtk_clk_pdev_probe, 109 .remove_new = mtk_clk_pdev_remove, 110 }; 111 module_platform_driver(clk_mt8173_mm_drv); 112 113 MODULE_DESCRIPTION("MediaTek MT8173 MultiMedia clocks driver"); 114 MODULE_LICENSE("GPL"); 115