1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Copyright (c) 2022 Collabora Ltd. 5 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6 */ 7 8 #include <dt-bindings/clock/mt8173-clk.h> 9 #include <linux/of_address.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include "clk-mtk.h" 13 #include "clk-pll.h" 14 15 #define REGOFF_REF2USB 0x8 16 #define REGOFF_HDMI_REF 0x40 17 18 #define MT8173_PLL_FMAX (3000UL * MHZ) 19 20 #define CON0_MT8173_RST_BAR BIT(24) 21 22 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 23 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 24 _pcw_shift, _div_table) { \ 25 .id = _id, \ 26 .name = _name, \ 27 .reg = _reg, \ 28 .pwr_reg = _pwr_reg, \ 29 .en_mask = _en_mask, \ 30 .flags = _flags, \ 31 .rst_bar_mask = CON0_MT8173_RST_BAR, \ 32 .fmax = MT8173_PLL_FMAX, \ 33 .pcwbits = _pcwbits, \ 34 .pd_reg = _pd_reg, \ 35 .pd_shift = _pd_shift, \ 36 .tuner_reg = _tuner_reg, \ 37 .pcw_reg = _pcw_reg, \ 38 .pcw_shift = _pcw_shift, \ 39 .div_table = _div_table, \ 40 } 41 42 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 43 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 44 _pcw_shift) \ 45 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 46 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 47 NULL) 48 49 static const struct mtk_pll_div_table mmpll_div_table[] = { 50 { .div = 0, .freq = MT8173_PLL_FMAX }, 51 { .div = 1, .freq = 1000000000 }, 52 { .div = 2, .freq = 702000000 }, 53 { .div = 3, .freq = 253500000 }, 54 { .div = 4, .freq = 126750000 }, 55 { } /* sentinel */ 56 }; 57 58 static const struct mtk_pll_data plls[] = { 59 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO, 60 21, 0x204, 24, 0x0, 0x204, 0), 61 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO, 62 21, 0x214, 24, 0x0, 0x214, 0), 63 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21, 64 0x220, 4, 0x0, 0x224, 0), 65 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7, 66 0x230, 4, 0x0, 0x234, 14), 67 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 68 0x244, 0, mmpll_div_table), 69 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0), 70 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0), 71 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0), 72 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0), 73 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0), 74 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0), 75 PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0), 76 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0), 77 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0), 78 }; 79 80 static const struct of_device_id of_match_clk_mt8173_apmixed[] = { 81 { .compatible = "mediatek,mt8173-apmixedsys" }, 82 { /* sentinel */ } 83 }; 84 85 static int clk_mt8173_apmixed_probe(struct platform_device *pdev) 86 { 87 struct device_node *node = pdev->dev.of_node; 88 struct clk_hw_onecell_data *clk_data; 89 void __iomem *base; 90 struct clk_hw *hw; 91 int r; 92 93 base = of_iomap(node, 0); 94 if (!base) 95 return PTR_ERR(base); 96 97 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 98 if (IS_ERR_OR_NULL(clk_data)) 99 return -ENOMEM; 100 101 r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 102 if (r) 103 goto free_clk_data; 104 105 hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_REF2USB); 106 if (IS_ERR(hw)) { 107 r = PTR_ERR(hw); 108 dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r); 109 goto unregister_plls; 110 } 111 clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw; 112 113 hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0, 114 base + REGOFF_HDMI_REF, 16, 3, 115 CLK_DIVIDER_POWER_OF_TWO, NULL); 116 clk_data->hws[CLK_APMIXED_HDMI_REF] = hw; 117 118 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 119 if (r) 120 goto unregister_ref2usb; 121 122 return 0; 123 124 unregister_ref2usb: 125 mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); 126 unregister_plls: 127 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); 128 free_clk_data: 129 mtk_free_clk_data(clk_data); 130 return r; 131 } 132 133 static int clk_mt8173_apmixed_remove(struct platform_device *pdev) 134 { 135 struct device_node *node = pdev->dev.of_node; 136 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); 137 138 of_clk_del_provider(node); 139 mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); 140 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); 141 mtk_free_clk_data(clk_data); 142 143 return 0; 144 } 145 146 static struct platform_driver clk_mt8173_apmixed_drv = { 147 .probe = clk_mt8173_apmixed_probe, 148 .remove = clk_mt8173_apmixed_remove, 149 .driver = { 150 .name = "clk-mt8173-apmixed", 151 .of_match_table = of_match_clk_mt8173_apmixed, 152 }, 153 }; 154 module_platform_driver(clk_mt8173_apmixed_drv); 155 156 MODULE_DESCRIPTION("MediaTek MT8173 apmixed clocks driver"); 157 MODULE_LICENSE("GPL"); 158