xref: /linux/drivers/clk/mediatek/clk-mt8167-vdec.c (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2020 MediaTek Inc.
4  * Copyright (c) 2020 BayLibre, SAS
5  * Author: James Liao <jamesjj.liao@mediatek.com>
6  *         Fabien Parent <fparent@baylibre.com>
7  */
8 
9 #include <linux/clk-provider.h>
10 #include <linux/platform_device.h>
11 
12 #include "clk-mtk.h"
13 #include "clk-gate.h"
14 
15 #include <dt-bindings/clock/mt8167-clk.h>
16 
17 static const struct mtk_gate_regs vdec0_cg_regs = {
18 	.set_ofs = 0x0,
19 	.clr_ofs = 0x4,
20 	.sta_ofs = 0x0,
21 };
22 
23 static const struct mtk_gate_regs vdec1_cg_regs = {
24 	.set_ofs = 0x8,
25 	.clr_ofs = 0xc,
26 	.sta_ofs = 0x8,
27 };
28 
29 #define GATE_VDEC0_I(_id, _name, _parent, _shift)			\
30 	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
31 
32 #define GATE_VDEC1_I(_id, _name, _parent, _shift)			\
33 	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
34 
35 static const struct mtk_gate vdec_clks[] = {
36 	/* VDEC0 */
37 	GATE_VDEC0_I(CLK_VDEC_CKEN, "vdec_cken", "rg_vdec", 0),
38 	/* VDEC1 */
39 	GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0),
40 };
41 
42 static const struct mtk_clk_desc vdec_desc = {
43 	.clks = vdec_clks,
44 	.num_clks = ARRAY_SIZE(vdec_clks),
45 };
46 
47 static const struct of_device_id of_match_clk_mt8167_vdec[] = {
48 	{ .compatible = "mediatek,mt8167-vdecsys", .data = &vdec_desc },
49 	{ /* sentinel */ }
50 };
51 MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_vdec);
52 
53 static struct platform_driver clk_mt8167_vdec_drv = {
54 	.probe = mtk_clk_simple_probe,
55 	.remove = mtk_clk_simple_remove,
56 	.driver = {
57 		.name = "clk-mt8167-vdecsys",
58 		.of_match_table = of_match_clk_mt8167_vdec,
59 	},
60 };
61 module_platform_driver(clk_mt8167_vdec_drv);
62 
63 MODULE_DESCRIPTION("MediaTek MT8167 Video Decoders clocks driver");
64 MODULE_LICENSE("GPL");
65