1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/slab.h> 11 #include <linux/mfd/syscon.h> 12 #include <dt-bindings/clock/mt8135-clk.h> 13 14 #include "clk-gate.h" 15 #include "clk-mtk.h" 16 #include "clk-pll.h" 17 18 static DEFINE_SPINLOCK(mt8135_clk_lock); 19 20 static const struct mtk_fixed_factor root_clk_alias[] __initconst = { 21 FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), 22 FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), 23 FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), 24 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), 25 }; 26 27 static const struct mtk_fixed_factor top_divs[] __initconst = { 28 FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2), 29 FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3), 30 FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5), 31 FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7), 32 33 FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2), 34 FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3), 35 FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5), 36 FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7), 37 FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26), 38 39 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 40 FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3), 41 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 42 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 43 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2), 44 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2), 45 46 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1), 47 FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2), 48 FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3), 49 FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4), 50 FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5), 51 FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6), 52 FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8), 53 FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12), 54 55 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1), 56 57 FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1), 58 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1), 59 60 FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1), 61 62 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2), 63 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4), 64 FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6), 65 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8), 66 FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10), 67 68 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2), 69 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4), 70 FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6), 71 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8), 72 73 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1), 74 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1), 75 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1), 76 FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2), 77 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1), 78 79 FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1), 80 FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4), 81 FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8), 82 FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16), 83 FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24), 84 85 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 86 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 87 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 88 89 FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1), 90 FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1), 91 92 FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1), 93 94 FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2), 95 FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3), 96 97 FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2), 98 FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4), 99 100 FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), 101 }; 102 103 static const char * const axi_parents[] __initconst = { 104 "clk26m", 105 "syspll_d3", 106 "syspll_d4", 107 "syspll_d6", 108 "univpll_d5", 109 "univpll2_d2", 110 "syspll_d3p5" 111 }; 112 113 static const char * const smi_parents[] __initconst = { 114 "clk26m", 115 "clkph_mck", 116 "syspll_d2p5", 117 "syspll_d3", 118 "syspll_d8", 119 "univpll_d5", 120 "univpll1_d2", 121 "univpll1_d6", 122 "mmpll_d3", 123 "mmpll_d4", 124 "mmpll_d5", 125 "mmpll_d6", 126 "mmpll_d7", 127 "vdecpll", 128 "lvdspll" 129 }; 130 131 static const char * const mfg_parents[] __initconst = { 132 "clk26m", 133 "univpll1_d4", 134 "syspll_d2", 135 "syspll_d2p5", 136 "syspll_d3", 137 "univpll_d5", 138 "univpll1_d2", 139 "mmpll_d2", 140 "mmpll_d3", 141 "mmpll_d4", 142 "mmpll_d5", 143 "mmpll_d6", 144 "mmpll_d7" 145 }; 146 147 static const char * const irda_parents[] __initconst = { 148 "clk26m", 149 "univpll2_d8", 150 "univpll1_d6" 151 }; 152 153 static const char * const cam_parents[] __initconst = { 154 "clk26m", 155 "syspll_d3", 156 "syspll_d3p5", 157 "syspll_d4", 158 "univpll_d5", 159 "univpll2_d2", 160 "univpll_d7", 161 "univpll1_d4" 162 }; 163 164 static const char * const aud_intbus_parents[] __initconst = { 165 "clk26m", 166 "syspll_d6", 167 "univpll_d10" 168 }; 169 170 static const char * const jpg_parents[] __initconst = { 171 "clk26m", 172 "syspll_d5", 173 "syspll_d4", 174 "syspll_d3", 175 "univpll_d7", 176 "univpll2_d2", 177 "univpll_d5" 178 }; 179 180 static const char * const disp_parents[] __initconst = { 181 "clk26m", 182 "syspll_d3p5", 183 "syspll_d3", 184 "univpll2_d2", 185 "univpll_d5", 186 "univpll1_d2", 187 "lvdspll", 188 "vdecpll" 189 }; 190 191 static const char * const msdc30_parents[] __initconst = { 192 "clk26m", 193 "syspll_d6", 194 "syspll_d5", 195 "univpll1_d4", 196 "univpll2_d4", 197 "msdcpll" 198 }; 199 200 static const char * const usb20_parents[] __initconst = { 201 "clk26m", 202 "univpll2_d6", 203 "univpll1_d10" 204 }; 205 206 static const char * const venc_parents[] __initconst = { 207 "clk26m", 208 "syspll_d3", 209 "syspll_d8", 210 "univpll_d5", 211 "univpll1_d6", 212 "mmpll_d4", 213 "mmpll_d5", 214 "mmpll_d6" 215 }; 216 217 static const char * const spi_parents[] __initconst = { 218 "clk26m", 219 "syspll_d6", 220 "syspll_d8", 221 "syspll_d10", 222 "univpll1_d6", 223 "univpll1_d8" 224 }; 225 226 static const char * const uart_parents[] __initconst = { 227 "clk26m", 228 "univpll2_d8" 229 }; 230 231 static const char * const mem_parents[] __initconst = { 232 "clk26m", 233 "clkph_mck" 234 }; 235 236 static const char * const camtg_parents[] __initconst = { 237 "clk26m", 238 "univpll_d26", 239 "univpll1_d6", 240 "syspll_d16", 241 "syspll_d8" 242 }; 243 244 static const char * const audio_parents[] __initconst = { 245 "clk26m", 246 "syspll_d24" 247 }; 248 249 static const char * const fix_parents[] __initconst = { 250 "rtc32k", 251 "clk26m", 252 "univpll_d5", 253 "univpll_d7", 254 "univpll1_d2", 255 "univpll1_d4", 256 "univpll1_d6", 257 "univpll1_d8" 258 }; 259 260 static const char * const vdec_parents[] __initconst = { 261 "clk26m", 262 "vdecpll", 263 "clkph_mck", 264 "syspll_d2p5", 265 "syspll_d3", 266 "syspll_d3p5", 267 "syspll_d4", 268 "syspll_d5", 269 "syspll_d6", 270 "syspll_d8", 271 "univpll1_d2", 272 "univpll2_d2", 273 "univpll_d7", 274 "univpll_d10", 275 "univpll2_d4", 276 "lvdspll" 277 }; 278 279 static const char * const ddrphycfg_parents[] __initconst = { 280 "clk26m", 281 "axi_sel", 282 "syspll_d12" 283 }; 284 285 static const char * const dpilvds_parents[] __initconst = { 286 "clk26m", 287 "lvdspll", 288 "lvdspll_d2", 289 "lvdspll_d4", 290 "lvdspll_d8" 291 }; 292 293 static const char * const pmicspi_parents[] __initconst = { 294 "clk26m", 295 "univpll2_d6", 296 "syspll_d8", 297 "syspll_d10", 298 "univpll1_d10", 299 "mempll_mck_d4", 300 "univpll_d26", 301 "syspll_d24" 302 }; 303 304 static const char * const smi_mfg_as_parents[] __initconst = { 305 "clk26m", 306 "smi_sel", 307 "mfg_sel", 308 "mem_sel" 309 }; 310 311 static const char * const gcpu_parents[] __initconst = { 312 "clk26m", 313 "syspll_d4", 314 "univpll_d7", 315 "syspll_d5", 316 "syspll_d6" 317 }; 318 319 static const char * const dpi1_parents[] __initconst = { 320 "clk26m", 321 "tvhdmi_h_ck", 322 "tvhdmi_d2", 323 "tvhdmi_d4" 324 }; 325 326 static const char * const cci_parents[] __initconst = { 327 "clk26m", 328 "mainpll_537p3m", 329 "univpll_d3", 330 "syspll_d2p5", 331 "syspll_d3", 332 "syspll_d5" 333 }; 334 335 static const char * const apll_parents[] __initconst = { 336 "clk26m", 337 "apll_ck", 338 "apll_d4", 339 "apll_d8", 340 "apll_d16", 341 "apll_d24" 342 }; 343 344 static const char * const hdmipll_parents[] __initconst = { 345 "clk26m", 346 "hdmitx_clkdig_cts", 347 "hdmitx_clkdig_d2", 348 "hdmitx_clkdig_d3" 349 }; 350 351 static const struct mtk_composite top_muxes[] __initconst = { 352 /* CLK_CFG_0 */ 353 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 354 0x0140, 0, 3, INVALID_MUX_GATE_BIT), 355 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15), 356 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23), 357 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31), 358 /* CLK_CFG_1 */ 359 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7), 360 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 361 0x0144, 8, 2, 15), 362 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23), 363 MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31), 364 /* CLK_CFG_2 */ 365 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7), 366 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15), 367 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23), 368 MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31), 369 /* CLK_CFG_3 */ 370 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7), 371 /* CLK_CFG_4 */ 372 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15), 373 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23), 374 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31), 375 /* CLK_CFG_6 */ 376 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7), 377 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15), 378 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31), 379 /* CLK_CFG_7 */ 380 MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7), 381 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15), 382 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 383 0x015c, 16, 2, 23), 384 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31), 385 /* CLK_CFG_8 */ 386 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7), 387 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15), 388 MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents, 389 0x0164, 16, 2, 23), 390 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31), 391 /* CLK_CFG_9 */ 392 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7), 393 MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15), 394 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23), 395 MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31), 396 }; 397 398 static const struct mtk_gate_regs infra_cg_regs = { 399 .set_ofs = 0x0040, 400 .clr_ofs = 0x0044, 401 .sta_ofs = 0x0048, 402 }; 403 404 #define GATE_ICG(_id, _name, _parent, _shift) { \ 405 .id = _id, \ 406 .name = _name, \ 407 .parent_name = _parent, \ 408 .regs = &infra_cg_regs, \ 409 .shift = _shift, \ 410 .ops = &mtk_clk_gate_ops_setclr, \ 411 } 412 413 static const struct mtk_gate infra_clks[] __initconst = { 414 GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), 415 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), 416 GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21), 417 GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20), 418 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), 419 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15), 420 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), 421 GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7), 422 GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6), 423 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5), 424 GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2), 425 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1), 426 GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0), 427 }; 428 429 static const struct mtk_gate_regs peri0_cg_regs = { 430 .set_ofs = 0x0008, 431 .clr_ofs = 0x0010, 432 .sta_ofs = 0x0018, 433 }; 434 435 static const struct mtk_gate_regs peri1_cg_regs = { 436 .set_ofs = 0x000c, 437 .clr_ofs = 0x0014, 438 .sta_ofs = 0x001c, 439 }; 440 441 #define GATE_PERI0(_id, _name, _parent, _shift) { \ 442 .id = _id, \ 443 .name = _name, \ 444 .parent_name = _parent, \ 445 .regs = &peri0_cg_regs, \ 446 .shift = _shift, \ 447 .ops = &mtk_clk_gate_ops_setclr, \ 448 } 449 450 #define GATE_PERI1(_id, _name, _parent, _shift) { \ 451 .id = _id, \ 452 .name = _name, \ 453 .parent_name = _parent, \ 454 .regs = &peri1_cg_regs, \ 455 .shift = _shift, \ 456 .ops = &mtk_clk_gate_ops_setclr, \ 457 } 458 459 static const struct mtk_gate peri_gates[] __initconst = { 460 /* PERI0 */ 461 GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31), 462 GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30), 463 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29), 464 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28), 465 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27), 466 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26), 467 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25), 468 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24), 469 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23), 470 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22), 471 GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21), 472 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20), 473 GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19), 474 GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18), 475 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17), 476 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16), 477 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15), 478 GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14), 479 GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13), 480 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), 481 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), 482 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), 483 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), 484 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8), 485 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7), 486 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6), 487 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5), 488 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4), 489 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3), 490 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2), 491 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), 492 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0), 493 /* PERI1 */ 494 GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8), 495 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7), 496 GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6), 497 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5), 498 GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4), 499 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3), 500 GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2), 501 GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1), 502 GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0), 503 }; 504 505 static const char * const uart_ck_sel_parents[] __initconst = { 506 "clk26m", 507 "uart_sel", 508 }; 509 510 static const struct mtk_composite peri_clks[] __initconst = { 511 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), 512 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), 513 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), 514 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), 515 }; 516 517 static void __init mtk_topckgen_init(struct device_node *node) 518 { 519 struct clk_hw_onecell_data *clk_data; 520 void __iomem *base; 521 int r; 522 523 base = of_iomap(node, 0); 524 if (!base) { 525 pr_err("%s(): ioremap failed\n", __func__); 526 return; 527 } 528 529 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 530 531 mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); 532 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 533 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, 534 &mt8135_clk_lock, clk_data); 535 536 clk_prepare_enable(clk_data->hws[CLK_TOP_CCI_SEL]->clk); 537 538 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 539 if (r) 540 pr_err("%s(): could not register clock provider: %d\n", 541 __func__, r); 542 } 543 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init); 544 545 static void __init mtk_infrasys_init(struct device_node *node) 546 { 547 struct clk_hw_onecell_data *clk_data; 548 int r; 549 550 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 551 552 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 553 clk_data); 554 555 clk_prepare_enable(clk_data->hws[CLK_INFRA_M4U]->clk); 556 557 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 558 if (r) 559 pr_err("%s(): could not register clock provider: %d\n", 560 __func__, r); 561 562 mtk_register_reset_controller(node, 2, 0x30); 563 } 564 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); 565 566 static void __init mtk_pericfg_init(struct device_node *node) 567 { 568 struct clk_hw_onecell_data *clk_data; 569 int r; 570 void __iomem *base; 571 572 base = of_iomap(node, 0); 573 if (!base) { 574 pr_err("%s(): ioremap failed\n", __func__); 575 return; 576 } 577 578 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 579 580 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), 581 clk_data); 582 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, 583 &mt8135_clk_lock, clk_data); 584 585 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 586 if (r) 587 pr_err("%s(): could not register clock provider: %d\n", 588 __func__, r); 589 590 mtk_register_reset_controller(node, 2, 0); 591 } 592 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); 593 594 #define MT8135_PLL_FMAX (2000 * MHZ) 595 #define CON0_MT8135_RST_BAR BIT(27) 596 597 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ 598 .id = _id, \ 599 .name = _name, \ 600 .reg = _reg, \ 601 .pwr_reg = _pwr_reg, \ 602 .en_mask = _en_mask, \ 603 .flags = _flags, \ 604 .rst_bar_mask = CON0_MT8135_RST_BAR, \ 605 .fmax = MT8135_PLL_FMAX, \ 606 .pcwbits = _pcwbits, \ 607 .pd_reg = _pd_reg, \ 608 .pd_shift = _pd_shift, \ 609 .tuner_reg = _tuner_reg, \ 610 .pcw_reg = _pcw_reg, \ 611 .pcw_shift = _pcw_shift, \ 612 } 613 614 static const struct mtk_pll_data plls[] = { 615 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0), 616 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0), 617 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0), 618 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9), 619 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0), 620 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0), 621 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0), 622 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), 623 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0), 624 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0), 625 }; 626 627 static void __init mtk_apmixedsys_init(struct device_node *node) 628 { 629 struct clk_hw_onecell_data *clk_data; 630 631 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 632 if (!clk_data) 633 return; 634 635 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 636 } 637 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys", 638 mtk_apmixedsys_init); 639