1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Sam Shih <sam.shih@mediatek.com> 5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include "clk-mtk.h" 14 #include "clk-gate.h" 15 #include "clk-mux.h" 16 17 #include <dt-bindings/clock/mt7986-clk.h> 18 #include <linux/clk.h> 19 20 static DEFINE_SPINLOCK(mt7986_clk_lock); 21 22 static const struct mtk_fixed_clk top_fixed_clks[] = { 23 FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), 24 FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000), 25 }; 26 27 static const struct mtk_fixed_factor top_divs[] = { 28 /* XTAL */ 29 FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), 30 FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), 31 FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), 32 /* MPLL */ 33 FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2), 34 FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4), 35 FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8), 36 FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16), 37 FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6), 38 /* MMPLL */ 39 FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2), 40 FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4), 41 FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8), 42 FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16), 43 FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24), 44 FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30), 45 /* APLL2 */ 46 FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4), 47 /* NET1PLL */ 48 FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4), 49 FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5), 50 FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10), 51 FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20), 52 FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16), 53 FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32), 54 /* NET2PLL */ 55 FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4), 56 FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8), 57 FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2), 58 /* WEDMCUPLL */ 59 FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1, 60 10), 61 }; 62 63 static const char *const nfi1x_parents[] __initconst = { "top_xtal", 64 "top_mmpll_d8", 65 "top_net1pll_d8_d2", 66 "top_net2pll_d3_d2", 67 "top_mpll_d4", 68 "top_mmpll_d8_d2", 69 "top_wedmcupll_d5_d2", 70 "top_mpll_d8" }; 71 72 static const char *const spinfi_parents[] __initconst = { 73 "top_xtal_d2", "top_xtal", "top_net1pll_d5_d4", 74 "top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2", 75 "top_mmpll_d3_d8", "top_mpll_d8" 76 }; 77 78 static const char *const spi_parents[] __initconst = { 79 "top_xtal", "top_mpll_d2", "top_mmpll_d8", 80 "top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4", 81 "top_mpll_d4", "top_wedmcupll_d5_d2" 82 }; 83 84 static const char *const uart_parents[] __initconst = { "top_xtal", 85 "top_mpll_d8", 86 "top_mpll_d8_d2" }; 87 88 static const char *const pwm_parents[] __initconst = { 89 "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4" 90 }; 91 92 static const char *const i2c_parents[] __initconst = { 93 "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4" 94 }; 95 96 static const char *const pextp_tl_ck_parents[] __initconst = { 97 "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k" 98 }; 99 100 static const char *const emmc_250m_parents[] __initconst = { 101 "top_xtal", "top_net1pll_d5_d2" 102 }; 103 104 static const char *const emmc_416m_parents[] __initconst = { "top_xtal", 105 "mpll" }; 106 107 static const char *const f_26m_adc_parents[] __initconst = { "top_xtal", 108 "top_mpll_d8_d2" }; 109 110 static const char *const dramc_md32_parents[] __initconst = { "top_xtal", 111 "top_mpll_d2" }; 112 113 static const char *const sysaxi_parents[] __initconst = { "top_xtal", 114 "top_net1pll_d8_d2", 115 "top_net2pll_d4" }; 116 117 static const char *const sysapb_parents[] __initconst = { "top_xtal", 118 "top_mpll_d3_d2", 119 "top_net2pll_d4_d2" }; 120 121 static const char *const arm_db_main_parents[] __initconst = { 122 "top_xtal", "top_net2pll_d3_d2" 123 }; 124 125 static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag", 126 "top_xtal" }; 127 128 static const char *const netsys_parents[] __initconst = { "top_xtal", 129 "top_mmpll_d4" }; 130 131 static const char *const netsys_500m_parents[] __initconst = { 132 "top_xtal", "top_net1pll_d5" 133 }; 134 135 static const char *const netsys_mcu_parents[] __initconst = { 136 "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4", 137 "top_net1pll_d5" 138 }; 139 140 static const char *const netsys_2x_parents[] __initconst = { 141 "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2" 142 }; 143 144 static const char *const sgm_325m_parents[] __initconst = { "top_xtal", 145 "sgmpll" }; 146 147 static const char *const sgm_reg_parents[] __initconst = { 148 "top_xtal", "top_net1pll_d8_d4" 149 }; 150 151 static const char *const a1sys_parents[] __initconst = { "top_xtal", 152 "top_apll2_d4" }; 153 154 static const char *const conn_mcusys_parents[] __initconst = { "top_xtal", 155 "top_mmpll_d2" }; 156 157 static const char *const eip_b_parents[] __initconst = { "top_xtal", 158 "net2pll" }; 159 160 static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2", 161 "top_mpll_d8_d2" }; 162 163 static const char *const a_tuner_parents[] __initconst = { "top_xtal", 164 "top_apll2_d4", 165 "top_mpll_d8_d2" }; 166 167 static const char *const u2u3_sys_parents[] __initconst = { 168 "top_xtal", "top_net1pll_d5_d4" 169 }; 170 171 static const char *const da_u2_refsel_parents[] __initconst = { 172 "top_xtal", "top_mmpll_u2phy" 173 }; 174 175 static const struct mtk_mux top_muxes[] = { 176 /* CLK_CFG_0 */ 177 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 178 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), 179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 180 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), 181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 182 0x004, 0x008, 16, 3, 23, 0x1C0, 2), 183 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 184 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), 185 /* CLK_CFG_1 */ 186 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 187 0x014, 0x018, 0, 2, 7, 0x1C0, 4), 188 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 189 0x014, 0x018, 8, 2, 15, 0x1C0, 5), 190 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 191 0x014, 0x018, 16, 2, 23, 0x1C0, 6), 192 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", 193 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 194 31, 0x1C0, 7), 195 /* CLK_CFG_2 */ 196 MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", 197 emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, 198 0x1C0, 8), 199 MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", 200 emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, 201 0x1C0, 9), 202 MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", 203 f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, 204 0x1C0, 10), 205 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", 206 f_26m_adc_parents, 0x020, 0x024, 0x028, 207 24, 1, 31, 0x1C0, 11, 208 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 209 /* CLK_CFG_3 */ 210 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", 211 dramc_md32_parents, 0x030, 0x034, 0x038, 212 0, 1, 7, 0x1C0, 12, 213 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 214 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", 215 sysaxi_parents, 0x030, 0x034, 0x038, 216 8, 2, 15, 0x1C0, 13, 217 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 218 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", 219 sysapb_parents, 0x030, 0x034, 0x038, 220 16, 2, 23, 0x1C0, 14, 221 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 222 MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", 223 arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 224 31, 0x1C0, 15), 225 /* CLK_CFG_4 */ 226 MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", 227 arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7, 228 0x1C0, 16), 229 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 230 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), 231 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", 232 netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 233 23, 0x1C0, 18), 234 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", 235 netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, 236 0x1C0, 19), 237 /* CLK_CFG_5 */ 238 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", 239 netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, 240 0x1C0, 20), 241 MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", 242 sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 243 0x1C0, 21), 244 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", 245 sgm_reg_parents, 0x050, 0x054, 0x058, 246 16, 1, 23, 0x1C0, 22, 247 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 248 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 249 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), 250 /* CLK_CFG_6 */ 251 MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", 252 conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7, 253 0x1C0, 24), 254 MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 255 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), 256 MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", 257 f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23, 258 0x1C0, 26), 259 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", 260 f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, 261 0x1C0, 27), 262 /* CLK_CFG_7 */ 263 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", 264 f_26m_adc_parents, 0x070, 0x074, 0x078, 265 0, 1, 7, 0x1C0, 28, 266 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 267 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 268 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), 269 MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", 270 a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23, 271 0x1C0, 30), 272 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 273 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), 274 /* CLK_CFG_8 */ 275 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", 276 u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7, 277 0x1C4, 1), 278 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", 279 u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15, 280 0x1C4, 2), 281 MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", 282 da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1, 283 23, 0x1C4, 3), 284 MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", 285 da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1, 286 31, 0x1C4, 4), 287 /* CLK_CFG_9 */ 288 MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", 289 sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7, 290 0x1C4, 5), 291 }; 292 293 static const struct mtk_clk_desc topck_desc = { 294 .fixed_clks = top_fixed_clks, 295 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 296 .factor_clks = top_divs, 297 .num_factor_clks = ARRAY_SIZE(top_divs), 298 .mux_clks = top_muxes, 299 .num_mux_clks = ARRAY_SIZE(top_muxes), 300 .clk_lock = &mt7986_clk_lock, 301 }; 302 303 static const struct of_device_id of_match_clk_mt7986_topckgen[] = { 304 { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc }, 305 { /* sentinel */ } 306 }; 307 308 static struct platform_driver clk_mt7986_topckgen_drv = { 309 .probe = mtk_clk_simple_probe, 310 .remove = mtk_clk_simple_remove, 311 .driver = { 312 .name = "clk-mt7986-topckgen", 313 .of_match_table = of_match_clk_mt7986_topckgen, 314 }, 315 }; 316 builtin_platform_driver(clk_mt7986_topckgen_drv); 317