1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Sam Shih <sam.shih@mediatek.com> 5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/platform_device.h> 10 11 #include "clk-mtk.h" 12 #include "clk-gate.h" 13 14 #include <dt-bindings/clock/mt7986-clk.h> 15 16 static const struct mtk_gate_regs sgmii0_cg_regs = { 17 .set_ofs = 0xe4, 18 .clr_ofs = 0xe4, 19 .sta_ofs = 0xe4, 20 }; 21 22 #define GATE_SGMII0(_id, _name, _parent, _shift) \ 23 GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 24 25 static const struct mtk_gate sgmii0_clks[] = { 26 GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2), 27 GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3), 28 GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4), 29 GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5), 30 }; 31 32 static const struct mtk_gate_regs sgmii1_cg_regs = { 33 .set_ofs = 0xe4, 34 .clr_ofs = 0xe4, 35 .sta_ofs = 0xe4, 36 }; 37 38 #define GATE_SGMII1(_id, _name, _parent, _shift) \ 39 GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 40 41 static const struct mtk_gate sgmii1_clks[] = { 42 GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2), 43 GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3), 44 GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4), 45 GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5), 46 }; 47 48 static const struct mtk_gate_regs eth_cg_regs = { 49 .set_ofs = 0x30, 50 .clr_ofs = 0x30, 51 .sta_ofs = 0x30, 52 }; 53 54 #define GATE_ETH(_id, _name, _parent, _shift) \ 55 GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 56 57 static const struct mtk_gate eth_clks[] = { 58 GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6), 59 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7), 60 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8), 61 GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14), 62 GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15), 63 }; 64 65 static const struct mtk_clk_desc eth_desc = { 66 .clks = eth_clks, 67 .num_clks = ARRAY_SIZE(eth_clks), 68 }; 69 70 static const struct mtk_clk_desc sgmii0_desc = { 71 .clks = sgmii0_clks, 72 .num_clks = ARRAY_SIZE(sgmii0_clks), 73 }; 74 75 static const struct mtk_clk_desc sgmii1_desc = { 76 .clks = sgmii1_clks, 77 .num_clks = ARRAY_SIZE(sgmii1_clks), 78 }; 79 80 static const struct of_device_id of_match_clk_mt7986_eth[] = { 81 { .compatible = "mediatek,mt7986-ethsys", .data = ð_desc }, 82 { .compatible = "mediatek,mt7986-sgmiisys_0", .data = &sgmii0_desc }, 83 { .compatible = "mediatek,mt7986-sgmiisys_1", .data = &sgmii1_desc }, 84 { /* sentinel */ } 85 }; 86 MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_eth); 87 88 static struct platform_driver clk_mt7986_eth_drv = { 89 .driver = { 90 .name = "clk-mt7986-eth", 91 .of_match_table = of_match_clk_mt7986_eth, 92 }, 93 .probe = mtk_clk_simple_probe, 94 .remove = mtk_clk_simple_remove, 95 }; 96 module_platform_driver(clk_mt7986_eth_drv); 97 98 MODULE_DESCRIPTION("MediaTek MT7986 Ethernet clocks driver"); 99 MODULE_LICENSE("GPL"); 100