1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include "clk-cpumux.h" 16 #include "clk-gate.h" 17 #include "clk-mtk.h" 18 #include "clk-pll.h" 19 20 #include <dt-bindings/clock/mt7629-clk.h> 21 22 #define MT7629_PLL_FMAX (2500UL * MHZ) 23 #define CON0_MT7629_RST_BAR BIT(24) 24 25 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 26 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 27 _pcw_shift, _div_table, _parent_name) { \ 28 .id = _id, \ 29 .name = _name, \ 30 .reg = _reg, \ 31 .pwr_reg = _pwr_reg, \ 32 .en_mask = _en_mask, \ 33 .flags = _flags, \ 34 .rst_bar_mask = CON0_MT7629_RST_BAR, \ 35 .fmax = MT7629_PLL_FMAX, \ 36 .pcwbits = _pcwbits, \ 37 .pd_reg = _pd_reg, \ 38 .pd_shift = _pd_shift, \ 39 .tuner_reg = _tuner_reg, \ 40 .pcw_reg = _pcw_reg, \ 41 .pcw_shift = _pcw_shift, \ 42 .div_table = _div_table, \ 43 .parent_name = _parent_name, \ 44 } 45 46 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 47 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 48 _pcw_shift) \ 49 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 50 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 51 NULL, "clk20m") 52 53 #define GATE_APMIXED(_id, _name, _parent, _shift) { \ 54 .id = _id, \ 55 .name = _name, \ 56 .parent_name = _parent, \ 57 .regs = &apmixed_cg_regs, \ 58 .shift = _shift, \ 59 .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 60 } 61 62 #define GATE_INFRA(_id, _name, _parent, _shift) { \ 63 .id = _id, \ 64 .name = _name, \ 65 .parent_name = _parent, \ 66 .regs = &infra_cg_regs, \ 67 .shift = _shift, \ 68 .ops = &mtk_clk_gate_ops_setclr, \ 69 } 70 71 #define GATE_PERI0(_id, _name, _parent, _shift) { \ 72 .id = _id, \ 73 .name = _name, \ 74 .parent_name = _parent, \ 75 .regs = &peri0_cg_regs, \ 76 .shift = _shift, \ 77 .ops = &mtk_clk_gate_ops_setclr, \ 78 } 79 80 #define GATE_PERI1(_id, _name, _parent, _shift) { \ 81 .id = _id, \ 82 .name = _name, \ 83 .parent_name = _parent, \ 84 .regs = &peri1_cg_regs, \ 85 .shift = _shift, \ 86 .ops = &mtk_clk_gate_ops_setclr, \ 87 } 88 89 static DEFINE_SPINLOCK(mt7629_clk_lock); 90 91 static const char * const axi_parents[] = { 92 "clkxtal", 93 "syspll1_d2", 94 "syspll_d5", 95 "syspll1_d4", 96 "univpll_d5", 97 "univpll2_d2", 98 "univpll_d7", 99 "dmpll_ck" 100 }; 101 102 static const char * const mem_parents[] = { 103 "clkxtal", 104 "dmpll_ck" 105 }; 106 107 static const char * const ddrphycfg_parents[] = { 108 "clkxtal", 109 "syspll1_d8" 110 }; 111 112 static const char * const eth_parents[] = { 113 "clkxtal", 114 "syspll1_d2", 115 "univpll1_d2", 116 "syspll1_d4", 117 "univpll_d5", 118 "sgmiipll_d2", 119 "univpll_d7", 120 "dmpll_ck" 121 }; 122 123 static const char * const pwm_parents[] = { 124 "clkxtal", 125 "univpll2_d4" 126 }; 127 128 static const char * const f10m_ref_parents[] = { 129 "clkxtal", 130 "sgmiipll_d2" 131 }; 132 133 static const char * const nfi_infra_parents[] = { 134 "clkxtal", 135 "clkxtal", 136 "clkxtal", 137 "clkxtal", 138 "clkxtal", 139 "clkxtal", 140 "univpll2_d8", 141 "univpll3_d4", 142 "syspll1_d8", 143 "univpll1_d8", 144 "syspll4_d2", 145 "syspll2_d4", 146 "univpll2_d4", 147 "univpll3_d2", 148 "syspll1_d4", 149 "syspll_d7" 150 }; 151 152 static const char * const flash_parents[] = { 153 "clkxtal", 154 "univpll_d80_d4", 155 "syspll2_d8", 156 "syspll3_d4", 157 "univpll3_d4", 158 "univpll1_d8", 159 "syspll2_d4", 160 "univpll2_d4" 161 }; 162 163 static const char * const uart_parents[] = { 164 "clkxtal", 165 "univpll2_d8" 166 }; 167 168 static const char * const spi0_parents[] = { 169 "clkxtal", 170 "syspll3_d2", 171 "clkxtal", 172 "syspll2_d4", 173 "syspll4_d2", 174 "univpll2_d4", 175 "univpll1_d8", 176 "clkxtal" 177 }; 178 179 static const char * const spi1_parents[] = { 180 "clkxtal", 181 "syspll3_d2", 182 "clkxtal", 183 "syspll4_d4", 184 "syspll4_d2", 185 "univpll2_d4", 186 "univpll1_d8", 187 "clkxtal" 188 }; 189 190 static const char * const msdc30_0_parents[] = { 191 "clkxtal", 192 "univpll2_d16", 193 "univ48m" 194 }; 195 196 static const char * const msdc30_1_parents[] = { 197 "clkxtal", 198 "univpll2_d16", 199 "univ48m", 200 "syspll2_d4", 201 "univpll2_d4", 202 "syspll_d7", 203 "syspll2_d2", 204 "univpll2_d2" 205 }; 206 207 static const char * const ap2wbmcu_parents[] = { 208 "clkxtal", 209 "syspll1_d2", 210 "univ48m", 211 "syspll1_d8", 212 "univpll2_d4", 213 "syspll_d7", 214 "syspll2_d2", 215 "univpll2_d2" 216 }; 217 218 static const char * const audio_parents[] = { 219 "clkxtal", 220 "syspll3_d4", 221 "syspll4_d4", 222 "syspll1_d16" 223 }; 224 225 static const char * const aud_intbus_parents[] = { 226 "clkxtal", 227 "syspll1_d4", 228 "syspll4_d2", 229 "dmpll_d4" 230 }; 231 232 static const char * const pmicspi_parents[] = { 233 "clkxtal", 234 "syspll1_d8", 235 "syspll3_d4", 236 "syspll1_d16", 237 "univpll3_d4", 238 "clkxtal", 239 "univpll2_d4", 240 "dmpll_d8" 241 }; 242 243 static const char * const scp_parents[] = { 244 "clkxtal", 245 "syspll1_d8", 246 "univpll2_d2", 247 "univpll2_d4" 248 }; 249 250 static const char * const atb_parents[] = { 251 "clkxtal", 252 "syspll1_d2", 253 "syspll_d5" 254 }; 255 256 static const char * const hif_parents[] = { 257 "clkxtal", 258 "syspll1_d2", 259 "univpll1_d2", 260 "syspll1_d4", 261 "univpll_d5", 262 "clk_null", 263 "univpll_d7" 264 }; 265 266 static const char * const sata_parents[] = { 267 "clkxtal", 268 "univpll2_d4" 269 }; 270 271 static const char * const usb20_parents[] = { 272 "clkxtal", 273 "univpll3_d4", 274 "syspll1_d8" 275 }; 276 277 static const char * const aud1_parents[] = { 278 "clkxtal" 279 }; 280 281 static const char * const irrx_parents[] = { 282 "clkxtal", 283 "syspll4_d16" 284 }; 285 286 static const char * const crypto_parents[] = { 287 "clkxtal", 288 "univpll_d3", 289 "univpll1_d2", 290 "syspll1_d2", 291 "univpll_d5", 292 "syspll_d5", 293 "univpll2_d2", 294 "syspll_d2" 295 }; 296 297 static const char * const gpt10m_parents[] = { 298 "clkxtal", 299 "clkxtal_d4" 300 }; 301 302 static const char * const peribus_ck_parents[] = { 303 "syspll1_d8", 304 "syspll1_d4" 305 }; 306 307 static const char * const infra_mux1_parents[] = { 308 "clkxtal", 309 "armpll", 310 "main_core_en", 311 "armpll" 312 }; 313 314 static const struct mtk_gate_regs apmixed_cg_regs = { 315 .set_ofs = 0x8, 316 .clr_ofs = 0x8, 317 .sta_ofs = 0x8, 318 }; 319 320 static const struct mtk_gate_regs infra_cg_regs = { 321 .set_ofs = 0x40, 322 .clr_ofs = 0x44, 323 .sta_ofs = 0x48, 324 }; 325 326 static const struct mtk_gate_regs peri0_cg_regs = { 327 .set_ofs = 0x8, 328 .clr_ofs = 0x10, 329 .sta_ofs = 0x18, 330 }; 331 332 static const struct mtk_gate_regs peri1_cg_regs = { 333 .set_ofs = 0xC, 334 .clr_ofs = 0x14, 335 .sta_ofs = 0x1C, 336 }; 337 338 static const struct mtk_pll_data plls[] = { 339 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0, 340 0, 21, 0x0204, 24, 0, 0x0204, 0), 341 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0, 342 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), 343 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0, 344 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), 345 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0, 346 0, 21, 0x0300, 1, 0, 0x0304, 0), 347 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0, 348 0, 21, 0x0314, 1, 0, 0x0318, 0), 349 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0, 350 0, 21, 0x0358, 1, 0, 0x035C, 0), 351 }; 352 353 static const struct mtk_gate apmixed_clks[] = { 354 GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), 355 }; 356 357 static const struct mtk_gate infra_clks[] = { 358 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0), 359 GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2), 360 GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4), 361 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18), 362 GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19), 363 }; 364 365 static const struct mtk_fixed_clk top_fixed_clks[] = { 366 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", 367 31250000), 368 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal", 369 31250000), 370 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal", 371 125000000), 372 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal", 373 125000000), 374 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal", 375 250000000), 376 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal", 377 250000000), 378 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal", 379 33333333), 380 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal", 381 50000000), 382 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal", 383 50000000), 384 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal", 385 50000000), 386 }; 387 388 static const struct mtk_fixed_factor top_divs[] = { 389 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4), 390 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500), 391 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125), 392 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500), 393 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1), 394 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1), 395 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024), 396 FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1), 397 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1), 398 FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1), 399 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1), 400 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 401 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4), 402 FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8), 403 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 404 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 405 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 406 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 407 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32), 408 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6), 409 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 410 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 411 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 412 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 413 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 414 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 415 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 416 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 417 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112), 418 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), 419 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 420 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 421 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16), 422 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 423 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 424 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 425 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 426 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48), 427 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 428 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 429 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 430 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80), 431 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 432 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320), 433 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25), 434 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2), 435 FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4), 436 FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1), 437 FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1), 438 FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1), 439 FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1), 440 FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1), 441 FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1), 442 FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1), 443 FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1), 444 FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1), 445 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4), 446 FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1), 447 FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1), 448 FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1), 449 FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1), 450 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1), 451 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1), 452 }; 453 454 static const struct mtk_gate peri_clks[] = { 455 /* PERI0 */ 456 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2), 457 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3), 458 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4), 459 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5), 460 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6), 461 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7), 462 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8), 463 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9), 464 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12), 465 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14), 466 GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17), 467 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18), 468 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19), 469 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20), 470 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22), 471 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23), 472 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28), 473 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29), 474 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30), 475 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31), 476 /* PERI1 */ 477 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1), 478 }; 479 480 static struct mtk_composite infra_muxes[] = { 481 /* INFRA_TOPCKGEN_CKMUXSEL */ 482 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 483 2, 2), 484 }; 485 486 static struct mtk_composite top_muxes[] = { 487 /* CLK_CFG_0 */ 488 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 489 0x040, 0, 3, 7), 490 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 491 0x040, 8, 1, 15), 492 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 493 0x040, 16, 1, 23), 494 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 495 0x040, 24, 3, 31), 496 /* CLK_CFG_1 */ 497 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 498 0x050, 0, 2, 7), 499 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents, 500 0x050, 8, 1, 15), 501 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents, 502 0x050, 16, 4, 23), 503 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 504 0x050, 24, 3, 31), 505 /* CLK_CFG_2 */ 506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 507 0x060, 0, 1, 7), 508 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents, 509 0x060, 8, 3, 15), 510 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents, 511 0x060, 16, 3, 23), 512 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents, 513 0x060, 24, 3, 31), 514 /* CLK_CFG_3 */ 515 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents, 516 0x070, 0, 3, 7), 517 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 518 0x070, 8, 3, 15), 519 MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents, 520 0x070, 16, 3, 23), 521 MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents, 522 0x070, 24, 3, 31), 523 /* CLK_CFG_4 */ 524 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 525 0x080, 0, 2, 7), 526 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 527 0x080, 8, 2, 15), 528 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 529 0x080, 16, 3, 23), 530 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 531 0x080, 24, 2, 31), 532 /* CLK_CFG_5 */ 533 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 534 0x090, 0, 2, 7), 535 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents, 536 0x090, 8, 3, 15), 537 MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents, 538 0x090, 16, 1, 23), 539 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents, 540 0x090, 24, 2, 31), 541 /* CLK_CFG_6 */ 542 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, 543 0x0A0, 0, 1, 7), 544 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents, 545 0x0A0, 8, 1, 15), 546 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents, 547 0x0A0, 16, 1, 23), 548 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents, 549 0x0A0, 24, 1, 31), 550 /* CLK_CFG_7 */ 551 MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents, 552 0x0B0, 0, 2, 7), 553 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents, 554 0x0B0, 8, 2, 15), 555 MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents, 556 0x0B0, 16, 2, 23), 557 MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents, 558 0x0B0, 24, 2, 31), 559 /* CLK_CFG_8 */ 560 MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents, 561 0x0C0, 0, 3, 7), 562 MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents, 563 0x0C0, 8, 1, 15), 564 MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents, 565 0x0C0, 16, 1, 23), 566 }; 567 568 static struct mtk_composite peri_muxes[] = { 569 /* PERI_GLOBALCON_CKSEL */ 570 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), 571 }; 572 573 static int mtk_topckgen_init(struct platform_device *pdev) 574 { 575 struct clk_hw_onecell_data *clk_data; 576 void __iomem *base; 577 struct device_node *node = pdev->dev.of_node; 578 579 base = devm_platform_ioremap_resource(pdev, 0); 580 if (IS_ERR(base)) 581 return PTR_ERR(base); 582 583 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 584 585 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 586 clk_data); 587 588 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), 589 clk_data); 590 591 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), 592 base, &mt7629_clk_lock, clk_data); 593 594 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); 595 clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); 596 clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk); 597 598 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 599 } 600 601 static int mtk_infrasys_init(struct platform_device *pdev) 602 { 603 struct device_node *node = pdev->dev.of_node; 604 struct clk_hw_onecell_data *clk_data; 605 606 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 607 608 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 609 clk_data); 610 611 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), 612 clk_data); 613 614 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 615 clk_data); 616 } 617 618 static int mtk_pericfg_init(struct platform_device *pdev) 619 { 620 struct clk_hw_onecell_data *clk_data; 621 void __iomem *base; 622 int r; 623 struct device_node *node = pdev->dev.of_node; 624 625 base = devm_platform_ioremap_resource(pdev, 0); 626 if (IS_ERR(base)) 627 return PTR_ERR(base); 628 629 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 630 631 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), 632 clk_data); 633 634 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, 635 &mt7629_clk_lock, clk_data); 636 637 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 638 if (r) 639 return r; 640 641 clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk); 642 643 return 0; 644 } 645 646 static int mtk_apmixedsys_init(struct platform_device *pdev) 647 { 648 struct clk_hw_onecell_data *clk_data; 649 struct device_node *node = pdev->dev.of_node; 650 651 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 652 if (!clk_data) 653 return -ENOMEM; 654 655 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), 656 clk_data); 657 658 mtk_clk_register_gates(node, apmixed_clks, 659 ARRAY_SIZE(apmixed_clks), clk_data); 660 661 clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); 662 clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk); 663 664 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 665 } 666 667 668 static const struct of_device_id of_match_clk_mt7629[] = { 669 { 670 .compatible = "mediatek,mt7629-apmixedsys", 671 .data = mtk_apmixedsys_init, 672 }, { 673 .compatible = "mediatek,mt7629-infracfg", 674 .data = mtk_infrasys_init, 675 }, { 676 .compatible = "mediatek,mt7629-topckgen", 677 .data = mtk_topckgen_init, 678 }, { 679 .compatible = "mediatek,mt7629-pericfg", 680 .data = mtk_pericfg_init, 681 }, { 682 /* sentinel */ 683 } 684 }; 685 686 static int clk_mt7629_probe(struct platform_device *pdev) 687 { 688 int (*clk_init)(struct platform_device *); 689 int r; 690 691 clk_init = of_device_get_match_data(&pdev->dev); 692 if (!clk_init) 693 return -EINVAL; 694 695 r = clk_init(pdev); 696 if (r) 697 dev_err(&pdev->dev, 698 "could not register clock provider: %s: %d\n", 699 pdev->name, r); 700 701 return r; 702 } 703 704 static struct platform_driver clk_mt7629_drv = { 705 .probe = clk_mt7629_probe, 706 .driver = { 707 .name = "clk-mt7629", 708 .of_match_table = of_match_clk_mt7629, 709 }, 710 }; 711 712 static int clk_mt7629_init(void) 713 { 714 return platform_driver_register(&clk_mt7629_drv); 715 } 716 717 arch_initcall(clk_mt7629_init); 718