1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 14 #include "clk-mtk.h" 15 #include "clk-gate.h" 16 17 #include <dt-bindings/clock/mt7629-clk.h> 18 19 #define GATE_PCIE(_id, _name, _parent, _shift) \ 20 GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 21 22 #define GATE_SSUSB(_id, _name, _parent, _shift) \ 23 GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 24 25 static const struct mtk_gate_regs pcie_cg_regs = { 26 .set_ofs = 0x30, 27 .clr_ofs = 0x30, 28 .sta_ofs = 0x30, 29 }; 30 31 static const struct mtk_gate_regs ssusb_cg_regs = { 32 .set_ofs = 0x30, 33 .clr_ofs = 0x30, 34 .sta_ofs = 0x30, 35 }; 36 37 static const struct mtk_gate ssusb_clks[] = { 38 GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p", 39 "to_u2_phy_1p", 0), 40 GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1), 41 GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5), 42 GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6), 43 GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7), 44 GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8), 45 }; 46 47 static const struct mtk_gate pcie_clks[] = { 48 GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12), 49 GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13), 50 GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14), 51 GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15), 52 GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16), 53 GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17), 54 GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18), 55 GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19), 56 GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20), 57 GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21), 58 GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22), 59 GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), 60 }; 61 62 static u16 rst_ofs[] = { 0x34, }; 63 64 static const struct mtk_clk_rst_desc clk_rst_desc = { 65 .version = MTK_RST_SIMPLE, 66 .rst_bank_ofs = rst_ofs, 67 .rst_bank_nr = ARRAY_SIZE(rst_ofs), 68 }; 69 70 static const struct mtk_clk_desc ssusb_desc = { 71 .clks = ssusb_clks, 72 .num_clks = ARRAY_SIZE(ssusb_clks), 73 .rst_desc = &clk_rst_desc, 74 }; 75 76 static const struct mtk_clk_desc pcie_desc = { 77 .clks = pcie_clks, 78 .num_clks = ARRAY_SIZE(pcie_clks), 79 .rst_desc = &clk_rst_desc, 80 }; 81 82 static const struct of_device_id of_match_clk_mt7629_hif[] = { 83 { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc }, 84 { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc }, 85 { /* sentinel */ } 86 }; 87 MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_hif); 88 89 static struct platform_driver clk_mt7629_hif_drv = { 90 .probe = mtk_clk_simple_probe, 91 .remove_new = mtk_clk_simple_remove, 92 .driver = { 93 .name = "clk-mt7629-hif", 94 .of_match_table = of_match_clk_mt7629_hif, 95 }, 96 }; 97 module_platform_driver(clk_mt7629_hif_drv); 98 MODULE_LICENSE("GPL"); 99