1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11
12 #include "clk-mtk.h"
13 #include "clk-gate.h"
14
15 #include <dt-bindings/clock/mt7629-clk.h>
16
17 #define GATE_ETH(_id, _name, _parent, _shift) \
18 GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
19
20 static const struct mtk_gate_regs eth_cg_regs = {
21 .set_ofs = 0x30,
22 .clr_ofs = 0x30,
23 .sta_ofs = 0x30,
24 };
25
26 static const struct mtk_gate eth_clks[] = {
27 GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
28 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
29 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
30 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
31 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
32 };
33
34 static const struct mtk_gate_regs sgmii_cg_regs = {
35 .set_ofs = 0xE4,
36 .clr_ofs = 0xE4,
37 .sta_ofs = 0xE4,
38 };
39
40 #define GATE_SGMII(_id, _name, _parent, _shift) \
41 GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
42
43 static const struct mtk_gate sgmii_clks[2][4] = {
44 {
45 GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
46 "ssusb_tx250m", 2),
47 GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
48 "ssusb_eq_rx250m", 3),
49 GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
50 "ssusb_cdr_ref", 4),
51 GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
52 "ssusb_cdr_fb", 5),
53 }, {
54 GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
55 "ssusb_tx250m", 2),
56 GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
57 "ssusb_eq_rx250m", 3),
58 GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
59 "ssusb_cdr_ref", 4),
60 GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
61 "ssusb_cdr_fb", 5),
62 }
63 };
64
65 static u16 rst_ofs[] = { 0x34, };
66
67 static const struct mtk_clk_rst_desc clk_rst_desc = {
68 .version = MTK_RST_SIMPLE,
69 .rst_bank_ofs = rst_ofs,
70 .rst_bank_nr = ARRAY_SIZE(rst_ofs),
71 };
72
clk_mt7629_ethsys_init(struct platform_device * pdev)73 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
74 {
75 struct clk_hw_onecell_data *clk_data;
76 struct device_node *node = pdev->dev.of_node;
77 int r;
78
79 clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
80 if (!clk_data)
81 return -ENOMEM;
82
83 mtk_clk_register_gates(&pdev->dev, node, eth_clks,
84 CLK_ETH_NR_CLK, clk_data);
85
86 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
87 if (r)
88 dev_err(&pdev->dev,
89 "could not register clock provider: %s: %d\n",
90 pdev->name, r);
91
92 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
93
94 return r;
95 }
96
clk_mt7629_sgmiisys_init(struct platform_device * pdev)97 static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
98 {
99 struct clk_hw_onecell_data *clk_data;
100 struct device_node *node = pdev->dev.of_node;
101 static int id;
102 int r;
103
104 clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
105 if (!clk_data)
106 return -ENOMEM;
107
108 mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
109 CLK_SGMII_NR_CLK, clk_data);
110
111 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
112 if (r)
113 dev_err(&pdev->dev,
114 "could not register clock provider: %s: %d\n",
115 pdev->name, r);
116
117 return r;
118 }
119
120 static const struct of_device_id of_match_clk_mt7629_eth[] = {
121 {
122 .compatible = "mediatek,mt7629-ethsys",
123 .data = clk_mt7629_ethsys_init,
124 }, {
125 .compatible = "mediatek,mt7629-sgmiisys",
126 .data = clk_mt7629_sgmiisys_init,
127 }, {
128 /* sentinel */
129 }
130 };
131 MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_eth);
132
clk_mt7629_eth_probe(struct platform_device * pdev)133 static int clk_mt7629_eth_probe(struct platform_device *pdev)
134 {
135 int (*clk_init)(struct platform_device *);
136 int r;
137
138 clk_init = of_device_get_match_data(&pdev->dev);
139 if (!clk_init)
140 return -EINVAL;
141
142 r = clk_init(pdev);
143 if (r)
144 dev_err(&pdev->dev,
145 "could not register clock provider: %s: %d\n",
146 pdev->name, r);
147
148 return r;
149 }
150
151 static struct platform_driver clk_mt7629_eth_drv = {
152 .probe = clk_mt7629_eth_probe,
153 .driver = {
154 .name = "clk-mt7629-eth",
155 .of_match_table = of_match_clk_mt7629_eth,
156 },
157 };
158
159 builtin_platform_driver(clk_mt7629_eth_drv);
160
161 MODULE_DESCRIPTION("MediaTek MT7629 Ethernet clocks driver");
162 MODULE_LICENSE("GPL");
163