xref: /linux/drivers/clk/mediatek/clk-mt7629-eth.c (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 MediaTek Inc.
4  * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5  *	   Ryder Lee <ryder.lee@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 
12 #include "clk-mtk.h"
13 #include "clk-gate.h"
14 
15 #include <dt-bindings/clock/mt7629-clk.h>
16 
17 #define GATE_ETH(_id, _name, _parent, _shift)			\
18 	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
19 
20 static const struct mtk_gate_regs eth_cg_regs = {
21 	.set_ofs = 0x30,
22 	.clr_ofs = 0x30,
23 	.sta_ofs = 0x30,
24 };
25 
26 static const struct mtk_gate eth_clks[] = {
27 	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
28 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
29 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
30 	GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
31 	GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
32 };
33 
34 static const struct mtk_gate_regs sgmii_cg_regs = {
35 	.set_ofs = 0xE4,
36 	.clr_ofs = 0xE4,
37 	.sta_ofs = 0xE4,
38 };
39 
40 #define GATE_SGMII(_id, _name, _parent, _shift)			\
41 	GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
42 
43 static const struct mtk_gate sgmii_clks[2][4] = {
44 	{
45 		GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
46 			   "ssusb_tx250m", 2),
47 		GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
48 			   "ssusb_eq_rx250m", 3),
49 		GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
50 			   "ssusb_cdr_ref", 4),
51 		GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
52 			   "ssusb_cdr_fb", 5),
53 	}, {
54 		GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
55 			   "ssusb_tx250m", 2),
56 		GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
57 			   "ssusb_eq_rx250m", 3),
58 		GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
59 			   "ssusb_cdr_ref", 4),
60 		GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
61 			   "ssusb_cdr_fb", 5),
62 	}
63 };
64 
65 static u16 rst_ofs[] = { 0x34, };
66 
67 static const struct mtk_clk_rst_desc clk_rst_desc = {
68 	.version = MTK_RST_SIMPLE,
69 	.rst_bank_ofs = rst_ofs,
70 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
71 };
72 
73 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
74 {
75 	struct clk_hw_onecell_data *clk_data;
76 	struct device_node *node = pdev->dev.of_node;
77 	int r;
78 
79 	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
80 
81 	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
82 			       CLK_ETH_NR_CLK, clk_data);
83 
84 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
85 	if (r)
86 		dev_err(&pdev->dev,
87 			"could not register clock provider: %s: %d\n",
88 			pdev->name, r);
89 
90 	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
91 
92 	return r;
93 }
94 
95 static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
96 {
97 	struct clk_hw_onecell_data *clk_data;
98 	struct device_node *node = pdev->dev.of_node;
99 	static int id;
100 	int r;
101 
102 	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
103 
104 	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
105 			       CLK_SGMII_NR_CLK, clk_data);
106 
107 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
108 	if (r)
109 		dev_err(&pdev->dev,
110 			"could not register clock provider: %s: %d\n",
111 			pdev->name, r);
112 
113 	return r;
114 }
115 
116 static const struct of_device_id of_match_clk_mt7629_eth[] = {
117 	{
118 		.compatible = "mediatek,mt7629-ethsys",
119 		.data = clk_mt7629_ethsys_init,
120 	}, {
121 		.compatible = "mediatek,mt7629-sgmiisys",
122 		.data = clk_mt7629_sgmiisys_init,
123 	}, {
124 		/* sentinel */
125 	}
126 };
127 MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_eth);
128 
129 static int clk_mt7629_eth_probe(struct platform_device *pdev)
130 {
131 	int (*clk_init)(struct platform_device *);
132 	int r;
133 
134 	clk_init = of_device_get_match_data(&pdev->dev);
135 	if (!clk_init)
136 		return -EINVAL;
137 
138 	r = clk_init(pdev);
139 	if (r)
140 		dev_err(&pdev->dev,
141 			"could not register clock provider: %s: %d\n",
142 			pdev->name, r);
143 
144 	return r;
145 }
146 
147 static struct platform_driver clk_mt7629_eth_drv = {
148 	.probe = clk_mt7629_eth_probe,
149 	.driver = {
150 		.name = "clk-mt7629-eth",
151 		.of_match_table = of_match_clk_mt7629_eth,
152 	},
153 };
154 
155 builtin_platform_driver(clk_mt7629_eth_drv);
156 MODULE_LICENSE("GPL");
157