1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Chen Zhong <chen.zhong@mediatek.com> 5 * Sean Wang <sean.wang@mediatek.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/platform_device.h> 10 11 #include "clk-cpumux.h" 12 #include "clk-gate.h" 13 #include "clk-mtk.h" 14 15 #include <dt-bindings/clock/mt7622-clk.h> 16 #include <linux/clk.h> /* for consumer */ 17 18 #define GATE_TOP0(_id, _name, _parent, _shift) \ 19 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 20 21 #define GATE_TOP1(_id, _name, _parent, _shift) \ 22 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 23 24 #define GATE_PERI0(_id, _name, _parent, _shift) \ 25 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 26 27 #define GATE_PERI0_AO(_id, _name, _parent, _shift) \ 28 GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \ 29 &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) 30 31 #define GATE_PERI1(_id, _name, _parent, _shift) \ 32 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 33 34 static DEFINE_SPINLOCK(mt7622_clk_lock); 35 36 static const char * const axi_parents[] = { 37 "clkxtal", 38 "syspll1_d2", 39 "syspll_d5", 40 "syspll1_d4", 41 "univpll_d5", 42 "univpll2_d2", 43 "univpll_d7" 44 }; 45 46 static const char * const mem_parents[] = { 47 "clkxtal", 48 "dmpll_ck" 49 }; 50 51 static const char * const ddrphycfg_parents[] = { 52 "clkxtal", 53 "syspll1_d8" 54 }; 55 56 static const char * const eth_parents[] = { 57 "clkxtal", 58 "syspll1_d2", 59 "univpll1_d2", 60 "syspll1_d4", 61 "univpll_d5", 62 "clk_null", 63 "univpll_d7" 64 }; 65 66 static const char * const pwm_parents[] = { 67 "clkxtal", 68 "univpll2_d4" 69 }; 70 71 static const char * const f10m_ref_parents[] = { 72 "clkxtal", 73 "syspll4_d16" 74 }; 75 76 static const char * const nfi_infra_parents[] = { 77 "clkxtal", 78 "clkxtal", 79 "clkxtal", 80 "clkxtal", 81 "clkxtal", 82 "clkxtal", 83 "clkxtal", 84 "clkxtal", 85 "univpll2_d8", 86 "syspll1_d8", 87 "univpll1_d8", 88 "syspll4_d2", 89 "univpll2_d4", 90 "univpll3_d2", 91 "syspll1_d4" 92 }; 93 94 static const char * const flash_parents[] = { 95 "clkxtal", 96 "univpll_d80_d4", 97 "syspll2_d8", 98 "syspll3_d4", 99 "univpll3_d4", 100 "univpll1_d8", 101 "syspll2_d4", 102 "univpll2_d4" 103 }; 104 105 static const char * const uart_parents[] = { 106 "clkxtal", 107 "univpll2_d8" 108 }; 109 110 static const char * const spi0_parents[] = { 111 "clkxtal", 112 "syspll3_d2", 113 "clkxtal", 114 "syspll2_d4", 115 "syspll4_d2", 116 "univpll2_d4", 117 "univpll1_d8", 118 "clkxtal" 119 }; 120 121 static const char * const spi1_parents[] = { 122 "clkxtal", 123 "syspll3_d2", 124 "clkxtal", 125 "syspll4_d4", 126 "syspll4_d2", 127 "univpll2_d4", 128 "univpll1_d8", 129 "clkxtal" 130 }; 131 132 static const char * const msdc30_0_parents[] = { 133 "clkxtal", 134 "univpll2_d16", 135 "univ48m" 136 }; 137 138 static const char * const a1sys_hp_parents[] = { 139 "clkxtal", 140 "aud1pll_ck", 141 "aud2pll_ck", 142 "clkxtal" 143 }; 144 145 static const char * const intdir_parents[] = { 146 "clkxtal", 147 "syspll_d2", 148 "univpll_d2", 149 "sgmiipll_ck" 150 }; 151 152 static const char * const aud_intbus_parents[] = { 153 "clkxtal", 154 "syspll1_d4", 155 "syspll4_d2", 156 "syspll3_d2" 157 }; 158 159 static const char * const pmicspi_parents[] = { 160 "clkxtal", 161 "clk_null", 162 "clk_null", 163 "clk_null", 164 "clk_null", 165 "univpll2_d16" 166 }; 167 168 static const char * const atb_parents[] = { 169 "clkxtal", 170 "syspll1_d2", 171 "syspll_d5" 172 }; 173 174 static const char * const audio_parents[] = { 175 "clkxtal", 176 "syspll3_d4", 177 "syspll4_d4", 178 "univpll1_d16" 179 }; 180 181 static const char * const usb20_parents[] = { 182 "clkxtal", 183 "univpll3_d4", 184 "syspll1_d8", 185 "clkxtal" 186 }; 187 188 static const char * const aud1_parents[] = { 189 "clkxtal", 190 "aud1pll_ck" 191 }; 192 193 static const char * const aud2_parents[] = { 194 "clkxtal", 195 "aud2pll_ck" 196 }; 197 198 static const char * const asm_l_parents[] = { 199 "clkxtal", 200 "syspll_d5", 201 "univpll2_d2", 202 "univpll2_d4" 203 }; 204 205 static const char * const apll1_ck_parents[] = { 206 "aud1_sel", 207 "aud2_sel" 208 }; 209 210 static const char * const peribus_ck_parents[] = { 211 "syspll1_d8", 212 "syspll1_d4" 213 }; 214 215 static const struct mtk_gate_regs top0_cg_regs = { 216 .set_ofs = 0x120, 217 .clr_ofs = 0x120, 218 .sta_ofs = 0x120, 219 }; 220 221 static const struct mtk_gate_regs top1_cg_regs = { 222 .set_ofs = 0x128, 223 .clr_ofs = 0x128, 224 .sta_ofs = 0x128, 225 }; 226 227 static const struct mtk_gate_regs peri0_cg_regs = { 228 .set_ofs = 0x8, 229 .clr_ofs = 0x10, 230 .sta_ofs = 0x18, 231 }; 232 233 static const struct mtk_gate_regs peri1_cg_regs = { 234 .set_ofs = 0xC, 235 .clr_ofs = 0x14, 236 .sta_ofs = 0x1C, 237 }; 238 239 static const struct mtk_fixed_clk top_fixed_clks[] = { 240 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", 241 31250000), 242 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal", 243 31250000), 244 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal", 245 125000000), 246 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal", 247 125000000), 248 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal", 249 250000000), 250 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal", 251 250000000), 252 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal", 253 33333333), 254 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal", 255 50000000), 256 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal", 257 50000000), 258 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal", 259 50000000), 260 }; 261 262 static const struct mtk_fixed_factor top_divs[] = { 263 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4), 264 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500), 265 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125), 266 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500), 267 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1), 268 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024), 269 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1), 270 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 271 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 272 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 273 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 274 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 275 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 276 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 277 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 278 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 279 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 280 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 281 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 282 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112), 283 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), 284 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 285 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 286 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 287 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16), 288 FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32), 289 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 290 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 291 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 292 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48), 293 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 294 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 295 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 296 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80), 297 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 298 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320), 299 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25), 300 FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1), 301 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2), 302 FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1), 303 FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1), 304 FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2), 305 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4), 306 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1), 307 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1), 308 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1), 309 }; 310 311 static const struct mtk_gate top_clks[] = { 312 /* TOP0 */ 313 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0), 314 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1), 315 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div", 316 2), 317 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div", 318 3), 319 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div", 320 4), 321 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div", 322 5), 323 324 /* TOP1 */ 325 GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0), 326 GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16), 327 }; 328 329 static const struct mtk_clk_divider top_adj_divs[] = { 330 DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel", 331 0x120, 24, 3), 332 DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel", 333 0x120, 28, 3), 334 DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel", 335 0x124, 0, 7), 336 DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel", 337 0x124, 8, 7), 338 DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck", 339 0x124, 16, 7), 340 DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel", 341 0x124, 24, 7), 342 DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel", 343 0x128, 8, 7), 344 DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel", 345 0x128, 24, 7), 346 }; 347 348 static const struct mtk_gate peri_clks[] = { 349 /* PERI0 */ 350 GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1), 351 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2), 352 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3), 353 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4), 354 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5), 355 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6), 356 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7), 357 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8), 358 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9), 359 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12), 360 GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13), 361 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14), 362 GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), 363 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18), 364 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19), 365 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20), 366 GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21), 367 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22), 368 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23), 369 GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24), 370 GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25), 371 GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26), 372 GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27), 373 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28), 374 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29), 375 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30), 376 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31), 377 378 /* PERI1 */ 379 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1), 380 GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2), 381 }; 382 383 static struct mtk_composite top_muxes[] = { 384 /* CLK_CFG_0 */ 385 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 386 0x040, 0, 3, 7, CLK_IS_CRITICAL), 387 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 388 0x040, 8, 1, 15, CLK_IS_CRITICAL), 389 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 390 0x040, 16, 1, 23, CLK_IS_CRITICAL), 391 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 392 0x040, 24, 3, 31), 393 394 /* CLK_CFG_1 */ 395 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 396 0x050, 0, 2, 7), 397 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents, 398 0x050, 8, 1, 15), 399 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents, 400 0x050, 16, 4, 23), 401 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 402 0x050, 24, 3, 31), 403 404 /* CLK_CFG_2 */ 405 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 406 0x060, 0, 1, 7), 407 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents, 408 0x060, 8, 3, 15), 409 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents, 410 0x060, 16, 3, 23), 411 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents, 412 0x060, 24, 3, 31), 413 414 /* CLK_CFG_3 */ 415 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents, 416 0x070, 0, 3, 7), 417 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents, 418 0x070, 8, 3, 15), 419 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, 420 0x070, 16, 2, 23), 421 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents, 422 0x070, 24, 2, 31), 423 424 /* CLK_CFG_4 */ 425 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 426 0x080, 0, 2, 7), 427 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 428 0x080, 8, 2, 15), 429 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 430 0x080, 16, 3, 23), 431 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents, 432 0x080, 24, 2, 31), 433 434 /* CLK_CFG_5 */ 435 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 436 0x090, 0, 2, 7), 437 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents, 438 0x090, 8, 3, 15), 439 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 440 0x090, 16, 2, 23), 441 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents, 442 0x090, 24, 2, 31), 443 444 /* CLK_CFG_6 */ 445 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, 446 0x0A0, 0, 1, 7), 447 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents, 448 0x0A0, 8, 1, 15), 449 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents, 450 0x0A0, 16, 1, 23), 451 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents, 452 0x0A0, 24, 1, 31), 453 454 /* CLK_CFG_7 */ 455 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, 456 0x0B0, 0, 2, 7), 457 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, 458 0x0B0, 8, 2, 15), 459 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, 460 0x0B0, 16, 2, 23), 461 462 /* CLK_AUDDIV_0 */ 463 MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents, 464 0x120, 6, 1), 465 MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents, 466 0x120, 7, 1), 467 MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents, 468 0x120, 8, 1), 469 MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents, 470 0x120, 9, 1), 471 MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents, 472 0x120, 10, 1), 473 MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents, 474 0x120, 11, 1), 475 }; 476 477 static struct mtk_composite peri_muxes[] = { 478 /* PERI_GLOBALCON_CKSEL */ 479 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), 480 }; 481 482 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 483 484 static const struct mtk_clk_rst_desc clk_rst_desc = { 485 .version = MTK_RST_SIMPLE, 486 .rst_bank_ofs = pericfg_rst_ofs, 487 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 488 }; 489 490 static const struct mtk_clk_desc topck_desc = { 491 .clks = top_clks, 492 .num_clks = ARRAY_SIZE(top_clks), 493 .fixed_clks = top_fixed_clks, 494 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 495 .factor_clks = top_divs, 496 .num_factor_clks = ARRAY_SIZE(top_divs), 497 .composite_clks = top_muxes, 498 .num_composite_clks = ARRAY_SIZE(top_muxes), 499 .divider_clks = top_adj_divs, 500 .num_divider_clks = ARRAY_SIZE(top_adj_divs), 501 .clk_lock = &mt7622_clk_lock, 502 }; 503 504 static const struct mtk_clk_desc peri_desc = { 505 .clks = peri_clks, 506 .num_clks = ARRAY_SIZE(peri_clks), 507 .composite_clks = peri_muxes, 508 .num_composite_clks = ARRAY_SIZE(peri_muxes), 509 .rst_desc = &clk_rst_desc, 510 .clk_lock = &mt7622_clk_lock, 511 }; 512 513 static const struct of_device_id of_match_clk_mt7622[] = { 514 { .compatible = "mediatek,mt7622-topckgen", .data = &topck_desc }, 515 { .compatible = "mediatek,mt7622-pericfg", .data = &peri_desc }, 516 { /* sentinel */ } 517 }; 518 MODULE_DEVICE_TABLE(of, of_match_clk_mt7622); 519 520 static struct platform_driver clk_mt7622_drv = { 521 .driver = { 522 .name = "clk-mt7622", 523 .of_match_table = of_match_clk_mt7622, 524 }, 525 .probe = mtk_clk_simple_probe, 526 .remove = mtk_clk_simple_remove, 527 }; 528 module_platform_driver(clk_mt7622_drv) 529 530 MODULE_DESCRIPTION("MediaTek MT7622 clocks driver"); 531 MODULE_LICENSE("GPL"); 532