11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22fc0a509SSean Wang /* 32fc0a509SSean Wang * Copyright (c) 2017 MediaTek Inc. 42fc0a509SSean Wang * Author: Chen Zhong <chen.zhong@mediatek.com> 52fc0a509SSean Wang * Sean Wang <sean.wang@mediatek.com> 62fc0a509SSean Wang */ 72fc0a509SSean Wang 82fc0a509SSean Wang #include <linux/clk-provider.h> 92fc0a509SSean Wang #include <linux/of.h> 102fc0a509SSean Wang #include <linux/of_address.h> 112fc0a509SSean Wang #include <linux/of_device.h> 122fc0a509SSean Wang #include <linux/platform_device.h> 132fc0a509SSean Wang 142fc0a509SSean Wang #include "clk-mtk.h" 152fc0a509SSean Wang #include "clk-gate.h" 162fc0a509SSean Wang 172fc0a509SSean Wang #include <dt-bindings/clock/mt7622-clk.h> 182fc0a509SSean Wang 194c85e20bSAngeloGioacchino Del Regno #define GATE_PCIE(_id, _name, _parent, _shift) \ 204c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 212fc0a509SSean Wang 224c85e20bSAngeloGioacchino Del Regno #define GATE_SSUSB(_id, _name, _parent, _shift) \ 234c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 242fc0a509SSean Wang 252fc0a509SSean Wang static const struct mtk_gate_regs pcie_cg_regs = { 262fc0a509SSean Wang .set_ofs = 0x30, 272fc0a509SSean Wang .clr_ofs = 0x30, 282fc0a509SSean Wang .sta_ofs = 0x30, 292fc0a509SSean Wang }; 302fc0a509SSean Wang 312fc0a509SSean Wang static const struct mtk_gate_regs ssusb_cg_regs = { 322fc0a509SSean Wang .set_ofs = 0x30, 332fc0a509SSean Wang .clr_ofs = 0x30, 342fc0a509SSean Wang .sta_ofs = 0x30, 352fc0a509SSean Wang }; 362fc0a509SSean Wang 372fc0a509SSean Wang static const struct mtk_gate ssusb_clks[] = { 382fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p", 392fc0a509SSean Wang "to_u2_phy_1p", 0), 402fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1), 412fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5), 422fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6), 432fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7), 442fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8), 452fc0a509SSean Wang }; 462fc0a509SSean Wang 472fc0a509SSean Wang static const struct mtk_gate pcie_clks[] = { 482fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12), 492fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13), 502fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14), 512fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15), 522fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16), 532fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17), 542fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18), 552fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19), 562fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20), 572fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21), 582fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22), 592fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), 602fc0a509SSean Wang GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26), 612fc0a509SSean Wang GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27), 622fc0a509SSean Wang GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28), 632fc0a509SSean Wang GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29), 642fc0a509SSean Wang GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), 652fc0a509SSean Wang }; 662fc0a509SSean Wang 67723e3671SRex-BC Chen static u16 rst_ofs[] = { 0x34, }; 68723e3671SRex-BC Chen 692d2a2900SRex-BC Chen static const struct mtk_clk_rst_desc clk_rst_desc = { 702d2a2900SRex-BC Chen .version = MTK_RST_SIMPLE, 71723e3671SRex-BC Chen .rst_bank_ofs = rst_ofs, 72723e3671SRex-BC Chen .rst_bank_nr = ARRAY_SIZE(rst_ofs), 732d2a2900SRex-BC Chen }; 742d2a2900SRex-BC Chen 750f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc ssusb_desc = { 760f69a423SAngeloGioacchino Del Regno .clks = ssusb_clks, 770f69a423SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(ssusb_clks), 780f69a423SAngeloGioacchino Del Regno .rst_desc = &clk_rst_desc, 792fc0a509SSean Wang }; 802fc0a509SSean Wang 810f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc pcie_desc = { 820f69a423SAngeloGioacchino Del Regno .clks = pcie_clks, 830f69a423SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(pcie_clks), 840f69a423SAngeloGioacchino Del Regno .rst_desc = &clk_rst_desc, 850f69a423SAngeloGioacchino Del Regno }; 862fc0a509SSean Wang 870f69a423SAngeloGioacchino Del Regno static const struct of_device_id of_match_clk_mt7622_hif[] = { 880f69a423SAngeloGioacchino Del Regno { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc }, 890f69a423SAngeloGioacchino Del Regno { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, 900f69a423SAngeloGioacchino Del Regno { /* sentinel */ } 910f69a423SAngeloGioacchino Del Regno }; 922fc0a509SSean Wang 932fc0a509SSean Wang static struct platform_driver clk_mt7622_hif_drv = { 940f69a423SAngeloGioacchino Del Regno .probe = mtk_clk_simple_probe, 950f69a423SAngeloGioacchino Del Regno .remove = mtk_clk_simple_remove, 962fc0a509SSean Wang .driver = { 972fc0a509SSean Wang .name = "clk-mt7622-hif", 982fc0a509SSean Wang .of_match_table = of_match_clk_mt7622_hif, 992fc0a509SSean Wang }, 1002fc0a509SSean Wang }; 101164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt7622_hif_drv); 102*a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 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