1*2fc0a509SSean Wang /* 2*2fc0a509SSean Wang * Copyright (c) 2017 MediaTek Inc. 3*2fc0a509SSean Wang * Author: Chen Zhong <chen.zhong@mediatek.com> 4*2fc0a509SSean Wang * Sean Wang <sean.wang@mediatek.com> 5*2fc0a509SSean Wang * 6*2fc0a509SSean Wang * This program is free software; you can redistribute it and/or modify 7*2fc0a509SSean Wang * it under the terms of the GNU General Public License version 2 as 8*2fc0a509SSean Wang * published by the Free Software Foundation. 9*2fc0a509SSean Wang * 10*2fc0a509SSean Wang * This program is distributed in the hope that it will be useful, 11*2fc0a509SSean Wang * but WITHOUT ANY WARRANTY; without even the implied warranty of 12*2fc0a509SSean Wang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*2fc0a509SSean Wang * GNU General Public License for more details. 14*2fc0a509SSean Wang */ 15*2fc0a509SSean Wang 16*2fc0a509SSean Wang #include <linux/clk-provider.h> 17*2fc0a509SSean Wang #include <linux/of.h> 18*2fc0a509SSean Wang #include <linux/of_address.h> 19*2fc0a509SSean Wang #include <linux/of_device.h> 20*2fc0a509SSean Wang #include <linux/platform_device.h> 21*2fc0a509SSean Wang 22*2fc0a509SSean Wang #include "clk-mtk.h" 23*2fc0a509SSean Wang #include "clk-gate.h" 24*2fc0a509SSean Wang 25*2fc0a509SSean Wang #include <dt-bindings/clock/mt7622-clk.h> 26*2fc0a509SSean Wang 27*2fc0a509SSean Wang #define GATE_PCIE(_id, _name, _parent, _shift) { \ 28*2fc0a509SSean Wang .id = _id, \ 29*2fc0a509SSean Wang .name = _name, \ 30*2fc0a509SSean Wang .parent_name = _parent, \ 31*2fc0a509SSean Wang .regs = &pcie_cg_regs, \ 32*2fc0a509SSean Wang .shift = _shift, \ 33*2fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 34*2fc0a509SSean Wang } 35*2fc0a509SSean Wang 36*2fc0a509SSean Wang #define GATE_SSUSB(_id, _name, _parent, _shift) { \ 37*2fc0a509SSean Wang .id = _id, \ 38*2fc0a509SSean Wang .name = _name, \ 39*2fc0a509SSean Wang .parent_name = _parent, \ 40*2fc0a509SSean Wang .regs = &ssusb_cg_regs, \ 41*2fc0a509SSean Wang .shift = _shift, \ 42*2fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 43*2fc0a509SSean Wang } 44*2fc0a509SSean Wang 45*2fc0a509SSean Wang static const struct mtk_gate_regs pcie_cg_regs = { 46*2fc0a509SSean Wang .set_ofs = 0x30, 47*2fc0a509SSean Wang .clr_ofs = 0x30, 48*2fc0a509SSean Wang .sta_ofs = 0x30, 49*2fc0a509SSean Wang }; 50*2fc0a509SSean Wang 51*2fc0a509SSean Wang static const struct mtk_gate_regs ssusb_cg_regs = { 52*2fc0a509SSean Wang .set_ofs = 0x30, 53*2fc0a509SSean Wang .clr_ofs = 0x30, 54*2fc0a509SSean Wang .sta_ofs = 0x30, 55*2fc0a509SSean Wang }; 56*2fc0a509SSean Wang 57*2fc0a509SSean Wang static const struct mtk_gate ssusb_clks[] = { 58*2fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p", 59*2fc0a509SSean Wang "to_u2_phy_1p", 0), 60*2fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1), 61*2fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5), 62*2fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6), 63*2fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7), 64*2fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8), 65*2fc0a509SSean Wang }; 66*2fc0a509SSean Wang 67*2fc0a509SSean Wang static const struct mtk_gate pcie_clks[] = { 68*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12), 69*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13), 70*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14), 71*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15), 72*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16), 73*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17), 74*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18), 75*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19), 76*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20), 77*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21), 78*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22), 79*2fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), 80*2fc0a509SSean Wang GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26), 81*2fc0a509SSean Wang GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27), 82*2fc0a509SSean Wang GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28), 83*2fc0a509SSean Wang GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29), 84*2fc0a509SSean Wang GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), 85*2fc0a509SSean Wang }; 86*2fc0a509SSean Wang 87*2fc0a509SSean Wang static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) 88*2fc0a509SSean Wang { 89*2fc0a509SSean Wang struct clk_onecell_data *clk_data; 90*2fc0a509SSean Wang struct device_node *node = pdev->dev.of_node; 91*2fc0a509SSean Wang int r; 92*2fc0a509SSean Wang 93*2fc0a509SSean Wang clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); 94*2fc0a509SSean Wang 95*2fc0a509SSean Wang mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), 96*2fc0a509SSean Wang clk_data); 97*2fc0a509SSean Wang 98*2fc0a509SSean Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 99*2fc0a509SSean Wang if (r) 100*2fc0a509SSean Wang dev_err(&pdev->dev, 101*2fc0a509SSean Wang "could not register clock provider: %s: %d\n", 102*2fc0a509SSean Wang pdev->name, r); 103*2fc0a509SSean Wang 104*2fc0a509SSean Wang mtk_register_reset_controller(node, 1, 0x34); 105*2fc0a509SSean Wang 106*2fc0a509SSean Wang return r; 107*2fc0a509SSean Wang } 108*2fc0a509SSean Wang 109*2fc0a509SSean Wang static int clk_mt7622_pciesys_init(struct platform_device *pdev) 110*2fc0a509SSean Wang { 111*2fc0a509SSean Wang struct clk_onecell_data *clk_data; 112*2fc0a509SSean Wang struct device_node *node = pdev->dev.of_node; 113*2fc0a509SSean Wang int r; 114*2fc0a509SSean Wang 115*2fc0a509SSean Wang clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); 116*2fc0a509SSean Wang 117*2fc0a509SSean Wang mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), 118*2fc0a509SSean Wang clk_data); 119*2fc0a509SSean Wang 120*2fc0a509SSean Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 121*2fc0a509SSean Wang if (r) 122*2fc0a509SSean Wang dev_err(&pdev->dev, 123*2fc0a509SSean Wang "could not register clock provider: %s: %d\n", 124*2fc0a509SSean Wang pdev->name, r); 125*2fc0a509SSean Wang 126*2fc0a509SSean Wang mtk_register_reset_controller(node, 1, 0x34); 127*2fc0a509SSean Wang 128*2fc0a509SSean Wang return r; 129*2fc0a509SSean Wang } 130*2fc0a509SSean Wang 131*2fc0a509SSean Wang static const struct of_device_id of_match_clk_mt7622_hif[] = { 132*2fc0a509SSean Wang { 133*2fc0a509SSean Wang .compatible = "mediatek,mt7622-pciesys", 134*2fc0a509SSean Wang .data = clk_mt7622_pciesys_init, 135*2fc0a509SSean Wang }, { 136*2fc0a509SSean Wang .compatible = "mediatek,mt7622-ssusbsys", 137*2fc0a509SSean Wang .data = clk_mt7622_ssusbsys_init, 138*2fc0a509SSean Wang }, { 139*2fc0a509SSean Wang /* sentinel */ 140*2fc0a509SSean Wang } 141*2fc0a509SSean Wang }; 142*2fc0a509SSean Wang 143*2fc0a509SSean Wang static int clk_mt7622_hif_probe(struct platform_device *pdev) 144*2fc0a509SSean Wang { 145*2fc0a509SSean Wang int (*clk_init)(struct platform_device *); 146*2fc0a509SSean Wang int r; 147*2fc0a509SSean Wang 148*2fc0a509SSean Wang clk_init = of_device_get_match_data(&pdev->dev); 149*2fc0a509SSean Wang if (!clk_init) 150*2fc0a509SSean Wang return -EINVAL; 151*2fc0a509SSean Wang 152*2fc0a509SSean Wang r = clk_init(pdev); 153*2fc0a509SSean Wang if (r) 154*2fc0a509SSean Wang dev_err(&pdev->dev, 155*2fc0a509SSean Wang "could not register clock provider: %s: %d\n", 156*2fc0a509SSean Wang pdev->name, r); 157*2fc0a509SSean Wang 158*2fc0a509SSean Wang return r; 159*2fc0a509SSean Wang } 160*2fc0a509SSean Wang 161*2fc0a509SSean Wang static struct platform_driver clk_mt7622_hif_drv = { 162*2fc0a509SSean Wang .probe = clk_mt7622_hif_probe, 163*2fc0a509SSean Wang .driver = { 164*2fc0a509SSean Wang .name = "clk-mt7622-hif", 165*2fc0a509SSean Wang .of_match_table = of_match_clk_mt7622_hif, 166*2fc0a509SSean Wang }, 167*2fc0a509SSean Wang }; 168*2fc0a509SSean Wang 169*2fc0a509SSean Wang builtin_platform_driver(clk_mt7622_hif_drv); 170