1*1802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22fc0a509SSean Wang /* 32fc0a509SSean Wang * Copyright (c) 2017 MediaTek Inc. 42fc0a509SSean Wang * Author: Chen Zhong <chen.zhong@mediatek.com> 52fc0a509SSean Wang * Sean Wang <sean.wang@mediatek.com> 62fc0a509SSean Wang */ 72fc0a509SSean Wang 82fc0a509SSean Wang #include <linux/clk-provider.h> 92fc0a509SSean Wang #include <linux/of.h> 102fc0a509SSean Wang #include <linux/of_address.h> 112fc0a509SSean Wang #include <linux/of_device.h> 122fc0a509SSean Wang #include <linux/platform_device.h> 132fc0a509SSean Wang 142fc0a509SSean Wang #include "clk-mtk.h" 152fc0a509SSean Wang #include "clk-gate.h" 162fc0a509SSean Wang 172fc0a509SSean Wang #include <dt-bindings/clock/mt7622-clk.h> 182fc0a509SSean Wang 192fc0a509SSean Wang #define GATE_PCIE(_id, _name, _parent, _shift) { \ 202fc0a509SSean Wang .id = _id, \ 212fc0a509SSean Wang .name = _name, \ 222fc0a509SSean Wang .parent_name = _parent, \ 232fc0a509SSean Wang .regs = &pcie_cg_regs, \ 242fc0a509SSean Wang .shift = _shift, \ 252fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 262fc0a509SSean Wang } 272fc0a509SSean Wang 282fc0a509SSean Wang #define GATE_SSUSB(_id, _name, _parent, _shift) { \ 292fc0a509SSean Wang .id = _id, \ 302fc0a509SSean Wang .name = _name, \ 312fc0a509SSean Wang .parent_name = _parent, \ 322fc0a509SSean Wang .regs = &ssusb_cg_regs, \ 332fc0a509SSean Wang .shift = _shift, \ 342fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 352fc0a509SSean Wang } 362fc0a509SSean Wang 372fc0a509SSean Wang static const struct mtk_gate_regs pcie_cg_regs = { 382fc0a509SSean Wang .set_ofs = 0x30, 392fc0a509SSean Wang .clr_ofs = 0x30, 402fc0a509SSean Wang .sta_ofs = 0x30, 412fc0a509SSean Wang }; 422fc0a509SSean Wang 432fc0a509SSean Wang static const struct mtk_gate_regs ssusb_cg_regs = { 442fc0a509SSean Wang .set_ofs = 0x30, 452fc0a509SSean Wang .clr_ofs = 0x30, 462fc0a509SSean Wang .sta_ofs = 0x30, 472fc0a509SSean Wang }; 482fc0a509SSean Wang 492fc0a509SSean Wang static const struct mtk_gate ssusb_clks[] = { 502fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p", 512fc0a509SSean Wang "to_u2_phy_1p", 0), 522fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1), 532fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5), 542fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6), 552fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7), 562fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8), 572fc0a509SSean Wang }; 582fc0a509SSean Wang 592fc0a509SSean Wang static const struct mtk_gate pcie_clks[] = { 602fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12), 612fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13), 622fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14), 632fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15), 642fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16), 652fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17), 662fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18), 672fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19), 682fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20), 692fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21), 702fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22), 712fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), 722fc0a509SSean Wang GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26), 732fc0a509SSean Wang GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27), 742fc0a509SSean Wang GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28), 752fc0a509SSean Wang GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29), 762fc0a509SSean Wang GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), 772fc0a509SSean Wang }; 782fc0a509SSean Wang 792fc0a509SSean Wang static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) 802fc0a509SSean Wang { 812fc0a509SSean Wang struct clk_onecell_data *clk_data; 822fc0a509SSean Wang struct device_node *node = pdev->dev.of_node; 832fc0a509SSean Wang int r; 842fc0a509SSean Wang 852fc0a509SSean Wang clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); 862fc0a509SSean Wang 872fc0a509SSean Wang mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), 882fc0a509SSean Wang clk_data); 892fc0a509SSean Wang 902fc0a509SSean Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 912fc0a509SSean Wang if (r) 922fc0a509SSean Wang dev_err(&pdev->dev, 932fc0a509SSean Wang "could not register clock provider: %s: %d\n", 942fc0a509SSean Wang pdev->name, r); 952fc0a509SSean Wang 962fc0a509SSean Wang mtk_register_reset_controller(node, 1, 0x34); 972fc0a509SSean Wang 982fc0a509SSean Wang return r; 992fc0a509SSean Wang } 1002fc0a509SSean Wang 1012fc0a509SSean Wang static int clk_mt7622_pciesys_init(struct platform_device *pdev) 1022fc0a509SSean Wang { 1032fc0a509SSean Wang struct clk_onecell_data *clk_data; 1042fc0a509SSean Wang struct device_node *node = pdev->dev.of_node; 1052fc0a509SSean Wang int r; 1062fc0a509SSean Wang 1072fc0a509SSean Wang clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); 1082fc0a509SSean Wang 1092fc0a509SSean Wang mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), 1102fc0a509SSean Wang clk_data); 1112fc0a509SSean Wang 1122fc0a509SSean Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1132fc0a509SSean Wang if (r) 1142fc0a509SSean Wang dev_err(&pdev->dev, 1152fc0a509SSean Wang "could not register clock provider: %s: %d\n", 1162fc0a509SSean Wang pdev->name, r); 1172fc0a509SSean Wang 1182fc0a509SSean Wang mtk_register_reset_controller(node, 1, 0x34); 1192fc0a509SSean Wang 1202fc0a509SSean Wang return r; 1212fc0a509SSean Wang } 1222fc0a509SSean Wang 1232fc0a509SSean Wang static const struct of_device_id of_match_clk_mt7622_hif[] = { 1242fc0a509SSean Wang { 1252fc0a509SSean Wang .compatible = "mediatek,mt7622-pciesys", 1262fc0a509SSean Wang .data = clk_mt7622_pciesys_init, 1272fc0a509SSean Wang }, { 1282fc0a509SSean Wang .compatible = "mediatek,mt7622-ssusbsys", 1292fc0a509SSean Wang .data = clk_mt7622_ssusbsys_init, 1302fc0a509SSean Wang }, { 1312fc0a509SSean Wang /* sentinel */ 1322fc0a509SSean Wang } 1332fc0a509SSean Wang }; 1342fc0a509SSean Wang 1352fc0a509SSean Wang static int clk_mt7622_hif_probe(struct platform_device *pdev) 1362fc0a509SSean Wang { 1372fc0a509SSean Wang int (*clk_init)(struct platform_device *); 1382fc0a509SSean Wang int r; 1392fc0a509SSean Wang 1402fc0a509SSean Wang clk_init = of_device_get_match_data(&pdev->dev); 1412fc0a509SSean Wang if (!clk_init) 1422fc0a509SSean Wang return -EINVAL; 1432fc0a509SSean Wang 1442fc0a509SSean Wang r = clk_init(pdev); 1452fc0a509SSean Wang if (r) 1462fc0a509SSean Wang dev_err(&pdev->dev, 1472fc0a509SSean Wang "could not register clock provider: %s: %d\n", 1482fc0a509SSean Wang pdev->name, r); 1492fc0a509SSean Wang 1502fc0a509SSean Wang return r; 1512fc0a509SSean Wang } 1522fc0a509SSean Wang 1532fc0a509SSean Wang static struct platform_driver clk_mt7622_hif_drv = { 1542fc0a509SSean Wang .probe = clk_mt7622_hif_probe, 1552fc0a509SSean Wang .driver = { 1562fc0a509SSean Wang .name = "clk-mt7622-hif", 1572fc0a509SSean Wang .of_match_table = of_match_clk_mt7622_hif, 1582fc0a509SSean Wang }, 1592fc0a509SSean Wang }; 1602fc0a509SSean Wang 1612fc0a509SSean Wang builtin_platform_driver(clk_mt7622_hif_drv); 162