11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22fc0a509SSean Wang /* 32fc0a509SSean Wang * Copyright (c) 2017 MediaTek Inc. 42fc0a509SSean Wang * Author: Chen Zhong <chen.zhong@mediatek.com> 52fc0a509SSean Wang * Sean Wang <sean.wang@mediatek.com> 62fc0a509SSean Wang */ 72fc0a509SSean Wang 82fc0a509SSean Wang #include <linux/clk-provider.h> 92fc0a509SSean Wang #include <linux/of.h> 102fc0a509SSean Wang #include <linux/of_address.h> 112fc0a509SSean Wang #include <linux/of_device.h> 122fc0a509SSean Wang #include <linux/platform_device.h> 132fc0a509SSean Wang 142fc0a509SSean Wang #include "clk-mtk.h" 152fc0a509SSean Wang #include "clk-gate.h" 162fc0a509SSean Wang 172fc0a509SSean Wang #include <dt-bindings/clock/mt7622-clk.h> 182fc0a509SSean Wang 192fc0a509SSean Wang #define GATE_PCIE(_id, _name, _parent, _shift) { \ 202fc0a509SSean Wang .id = _id, \ 212fc0a509SSean Wang .name = _name, \ 222fc0a509SSean Wang .parent_name = _parent, \ 232fc0a509SSean Wang .regs = &pcie_cg_regs, \ 242fc0a509SSean Wang .shift = _shift, \ 252fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 262fc0a509SSean Wang } 272fc0a509SSean Wang 282fc0a509SSean Wang #define GATE_SSUSB(_id, _name, _parent, _shift) { \ 292fc0a509SSean Wang .id = _id, \ 302fc0a509SSean Wang .name = _name, \ 312fc0a509SSean Wang .parent_name = _parent, \ 322fc0a509SSean Wang .regs = &ssusb_cg_regs, \ 332fc0a509SSean Wang .shift = _shift, \ 342fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 352fc0a509SSean Wang } 362fc0a509SSean Wang 372fc0a509SSean Wang static const struct mtk_gate_regs pcie_cg_regs = { 382fc0a509SSean Wang .set_ofs = 0x30, 392fc0a509SSean Wang .clr_ofs = 0x30, 402fc0a509SSean Wang .sta_ofs = 0x30, 412fc0a509SSean Wang }; 422fc0a509SSean Wang 432fc0a509SSean Wang static const struct mtk_gate_regs ssusb_cg_regs = { 442fc0a509SSean Wang .set_ofs = 0x30, 452fc0a509SSean Wang .clr_ofs = 0x30, 462fc0a509SSean Wang .sta_ofs = 0x30, 472fc0a509SSean Wang }; 482fc0a509SSean Wang 492fc0a509SSean Wang static const struct mtk_gate ssusb_clks[] = { 502fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p", 512fc0a509SSean Wang "to_u2_phy_1p", 0), 522fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1), 532fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5), 542fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6), 552fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7), 562fc0a509SSean Wang GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8), 572fc0a509SSean Wang }; 582fc0a509SSean Wang 592fc0a509SSean Wang static const struct mtk_gate pcie_clks[] = { 602fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12), 612fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13), 622fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14), 632fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15), 642fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16), 652fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17), 662fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18), 672fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19), 682fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20), 692fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21), 702fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22), 712fc0a509SSean Wang GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), 722fc0a509SSean Wang GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26), 732fc0a509SSean Wang GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27), 742fc0a509SSean Wang GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28), 752fc0a509SSean Wang GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29), 762fc0a509SSean Wang GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), 772fc0a509SSean Wang }; 782fc0a509SSean Wang 79723e3671SRex-BC Chen static u16 rst_ofs[] = { 0x34, }; 80723e3671SRex-BC Chen 812d2a2900SRex-BC Chen static const struct mtk_clk_rst_desc clk_rst_desc = { 822d2a2900SRex-BC Chen .version = MTK_RST_SIMPLE, 83723e3671SRex-BC Chen .rst_bank_ofs = rst_ofs, 84723e3671SRex-BC Chen .rst_bank_nr = ARRAY_SIZE(rst_ofs), 852d2a2900SRex-BC Chen }; 862d2a2900SRex-BC Chen 87*0f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc ssusb_desc = { 88*0f69a423SAngeloGioacchino Del Regno .clks = ssusb_clks, 89*0f69a423SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(ssusb_clks), 90*0f69a423SAngeloGioacchino Del Regno .rst_desc = &clk_rst_desc, 912fc0a509SSean Wang }; 922fc0a509SSean Wang 93*0f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc pcie_desc = { 94*0f69a423SAngeloGioacchino Del Regno .clks = pcie_clks, 95*0f69a423SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(pcie_clks), 96*0f69a423SAngeloGioacchino Del Regno .rst_desc = &clk_rst_desc, 97*0f69a423SAngeloGioacchino Del Regno }; 982fc0a509SSean Wang 99*0f69a423SAngeloGioacchino Del Regno static const struct of_device_id of_match_clk_mt7622_hif[] = { 100*0f69a423SAngeloGioacchino Del Regno { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc }, 101*0f69a423SAngeloGioacchino Del Regno { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, 102*0f69a423SAngeloGioacchino Del Regno { /* sentinel */ } 103*0f69a423SAngeloGioacchino Del Regno }; 1042fc0a509SSean Wang 1052fc0a509SSean Wang static struct platform_driver clk_mt7622_hif_drv = { 106*0f69a423SAngeloGioacchino Del Regno .probe = mtk_clk_simple_probe, 107*0f69a423SAngeloGioacchino Del Regno .remove = mtk_clk_simple_remove, 1082fc0a509SSean Wang .driver = { 1092fc0a509SSean Wang .name = "clk-mt7622-hif", 1102fc0a509SSean Wang .of_match_table = of_match_clk_mt7622_hif, 1112fc0a509SSean Wang }, 1122fc0a509SSean Wang }; 1132fc0a509SSean Wang 1142fc0a509SSean Wang builtin_platform_driver(clk_mt7622_hif_drv); 115