1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Chen Zhong <chen.zhong@mediatek.com> 5 * Sean Wang <sean.wang@mediatek.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/platform_device.h> 10 11 #include "clk-mtk.h" 12 #include "clk-gate.h" 13 14 #include <dt-bindings/clock/mt7622-clk.h> 15 16 #define GATE_ETH(_id, _name, _parent, _shift) \ 17 GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 18 19 static const struct mtk_gate_regs eth_cg_regs = { 20 .set_ofs = 0x30, 21 .clr_ofs = 0x30, 22 .sta_ofs = 0x30, 23 }; 24 25 static const struct mtk_gate eth_clks[] = { 26 GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), 27 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), 28 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 29 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 30 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), 31 }; 32 33 static const struct mtk_gate_regs sgmii_cg_regs = { 34 .set_ofs = 0xE4, 35 .clr_ofs = 0xE4, 36 .sta_ofs = 0xE4, 37 }; 38 39 #define GATE_SGMII(_id, _name, _parent, _shift) \ 40 GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 41 42 static const struct mtk_gate sgmii_clks[] = { 43 GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", 44 "ssusb_tx250m", 2), 45 GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en", 46 "ssusb_eq_rx250m", 3), 47 GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref", 48 "ssusb_cdr_ref", 4), 49 GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb", 50 "ssusb_cdr_fb", 5), 51 }; 52 53 static u16 rst_ofs[] = { 0x34, }; 54 55 static const struct mtk_clk_rst_desc clk_rst_desc = { 56 .version = MTK_RST_SIMPLE, 57 .rst_bank_ofs = rst_ofs, 58 .rst_bank_nr = ARRAY_SIZE(rst_ofs), 59 }; 60 61 static const struct mtk_clk_desc eth_desc = { 62 .clks = eth_clks, 63 .num_clks = ARRAY_SIZE(eth_clks), 64 .rst_desc = &clk_rst_desc, 65 }; 66 67 static const struct mtk_clk_desc sgmii_desc = { 68 .clks = sgmii_clks, 69 .num_clks = ARRAY_SIZE(sgmii_clks), 70 }; 71 72 static const struct of_device_id of_match_clk_mt7622_eth[] = { 73 { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc }, 74 { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, 75 { /* sentinel */ } 76 }; 77 MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_eth); 78 79 static struct platform_driver clk_mt7622_eth_drv = { 80 .probe = mtk_clk_simple_probe, 81 .remove = mtk_clk_simple_remove, 82 .driver = { 83 .name = "clk-mt7622-eth", 84 .of_match_table = of_match_clk_mt7622_eth, 85 }, 86 }; 87 module_platform_driver(clk_mt7622_eth_drv); 88 89 MODULE_DESCRIPTION("MediaTek MT7622 Ethernet clocks driver"); 90 MODULE_LICENSE("GPL"); 91