1710774e0Smtk01761 // SPDX-License-Identifier: GPL-2.0 2710774e0Smtk01761 /* 3710774e0Smtk01761 * Copyright (c) 2019 MediaTek Inc. 4710774e0Smtk01761 * Author: Wendell Lin <wendell.lin@mediatek.com> 5710774e0Smtk01761 */ 6710774e0Smtk01761 7f09b9460SMiles Chen #include <linux/module.h> 8710774e0Smtk01761 #include <linux/clk-provider.h> 9710774e0Smtk01761 #include <linux/platform_device.h> 10710774e0Smtk01761 11710774e0Smtk01761 #include "clk-mtk.h" 12710774e0Smtk01761 #include "clk-gate.h" 13710774e0Smtk01761 14710774e0Smtk01761 #include <dt-bindings/clock/mt6779-clk.h> 15710774e0Smtk01761 16710774e0Smtk01761 static const struct mtk_gate_regs vdec0_cg_regs = { 17710774e0Smtk01761 .set_ofs = 0x0000, 18710774e0Smtk01761 .clr_ofs = 0x0004, 19710774e0Smtk01761 .sta_ofs = 0x0000, 20710774e0Smtk01761 }; 21710774e0Smtk01761 22710774e0Smtk01761 static const struct mtk_gate_regs vdec1_cg_regs = { 23710774e0Smtk01761 .set_ofs = 0x0008, 24710774e0Smtk01761 .clr_ofs = 0x000c, 25710774e0Smtk01761 .sta_ofs = 0x0008, 26710774e0Smtk01761 }; 27710774e0Smtk01761 28710774e0Smtk01761 #define GATE_VDEC0_I(_id, _name, _parent, _shift) \ 29710774e0Smtk01761 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \ 30710774e0Smtk01761 &mtk_clk_gate_ops_setclr_inv) 31710774e0Smtk01761 #define GATE_VDEC1_I(_id, _name, _parent, _shift) \ 32710774e0Smtk01761 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \ 33710774e0Smtk01761 &mtk_clk_gate_ops_setclr_inv) 34710774e0Smtk01761 35710774e0Smtk01761 static const struct mtk_gate vdec_clks[] = { 36710774e0Smtk01761 /* VDEC0 */ 37710774e0Smtk01761 GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_cken", "vdec_sel", 0), 38710774e0Smtk01761 /* VDEC1 */ 39710774e0Smtk01761 GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1_cken", "vdec_sel", 0), 40710774e0Smtk01761 }; 41710774e0Smtk01761 42dc6fdd8aSMiles Chen static const struct mtk_clk_desc vdec_desc = { 43dc6fdd8aSMiles Chen .clks = vdec_clks, 44dc6fdd8aSMiles Chen .num_clks = ARRAY_SIZE(vdec_clks), 45710774e0Smtk01761 }; 46710774e0Smtk01761 47dc6fdd8aSMiles Chen static const struct of_device_id of_match_clk_mt6779_vdec[] = { 48710774e0Smtk01761 { 49dc6fdd8aSMiles Chen .compatible = "mediatek,mt6779-vdecsys", 50dc6fdd8aSMiles Chen .data = &vdec_desc, 51dc6fdd8aSMiles Chen }, { 52dc6fdd8aSMiles Chen /* sentinel */ 53710774e0Smtk01761 } 54dc6fdd8aSMiles Chen }; 5565c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_vdec); 56710774e0Smtk01761 57710774e0Smtk01761 static struct platform_driver clk_mt6779_vdec_drv = { 58dc6fdd8aSMiles Chen .probe = mtk_clk_simple_probe, 59*f00b45dbSUwe Kleine-König .remove = mtk_clk_simple_remove, 60710774e0Smtk01761 .driver = { 61710774e0Smtk01761 .name = "clk-mt6779-vdec", 62710774e0Smtk01761 .of_match_table = of_match_clk_mt6779_vdec, 63710774e0Smtk01761 }, 64710774e0Smtk01761 }; 65710774e0Smtk01761 66f09b9460SMiles Chen module_platform_driver(clk_mt6779_vdec_drv); 67f5100c41SAngeloGioacchino Del Regno 68f5100c41SAngeloGioacchino Del Regno MODULE_DESCRIPTION("MediaTek MT6779 Video Decoders clocks driver"); 69f09b9460SMiles Chen MODULE_LICENSE("GPL"); 70