xref: /linux/drivers/clk/mediatek/clk-mt6779-ipe.c (revision 82e8d723e9e6698572098bf2976223d5069b34b5)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2019 MediaTek Inc.
4  * Author: Wendell Lin <wendell.lin@mediatek.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
9 #include <dt-bindings/clock/mt6779-clk.h>
10 
11 #include "clk-mtk.h"
12 #include "clk-gate.h"
13 
14 static const struct mtk_gate_regs ipe_cg_regs = {
15 	.set_ofs = 0x0004,
16 	.clr_ofs = 0x0008,
17 	.sta_ofs = 0x0000,
18 };
19 
20 #define GATE_IPE(_id, _name, _parent, _shift)			\
21 	GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift,	\
22 		&mtk_clk_gate_ops_setclr)
23 
24 static const struct mtk_gate ipe_clks[] = {
25 	GATE_IPE(CLK_IPE_LARB7, "ipe_larb7", "ipe_sel", 0),
26 	GATE_IPE(CLK_IPE_LARB8, "ipe_larb8", "ipe_sel", 1),
27 	GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
28 	GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
29 	GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
30 	GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
31 	GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
32 };
33 
34 static const struct of_device_id of_match_clk_mt6779_ipe[] = {
35 	{ .compatible = "mediatek,mt6779-ipesys", },
36 	{}
37 };
38 
39 static int clk_mt6779_ipe_probe(struct platform_device *pdev)
40 {
41 	struct clk_onecell_data *clk_data;
42 	struct device_node *node = pdev->dev.of_node;
43 
44 	clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK);
45 
46 	mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks),
47 			       clk_data);
48 
49 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
50 }
51 
52 static struct platform_driver clk_mt6779_ipe_drv = {
53 	.probe = clk_mt6779_ipe_probe,
54 	.driver = {
55 		.name = "clk-mt6779-ipe",
56 		.of_match_table = of_match_clk_mt6779_ipe,
57 	},
58 };
59 
60 builtin_platform_driver(clk_mt6779_ipe_drv);
61