1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Owen Chen <owen.chen@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/slab.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 14 #include "clk-gate.h" 15 #include "clk-mtk.h" 16 #include "clk-mux.h" 17 #include "clk-pll.h" 18 19 #include <dt-bindings/clock/mt6765-clk.h> 20 21 /*fmeter div select 4*/ 22 #define _DIV4_ 1 23 24 static DEFINE_SPINLOCK(mt6765_clk_lock); 25 26 /* Total 12 subsys */ 27 static void __iomem *cksys_base; 28 static void __iomem *apmixed_base; 29 30 /* CKSYS */ 31 #define CLK_SCP_CFG_0 (cksys_base + 0x200) 32 #define CLK_SCP_CFG_1 (cksys_base + 0x204) 33 34 /* CG */ 35 #define AP_PLL_CON3 (apmixed_base + 0x0C) 36 #define PLLON_CON0 (apmixed_base + 0x44) 37 #define PLLON_CON1 (apmixed_base + 0x48) 38 39 /* clk cfg update */ 40 #define CLK_CFG_0 0x40 41 #define CLK_CFG_0_SET 0x44 42 #define CLK_CFG_0_CLR 0x48 43 #define CLK_CFG_1 0x50 44 #define CLK_CFG_1_SET 0x54 45 #define CLK_CFG_1_CLR 0x58 46 #define CLK_CFG_2 0x60 47 #define CLK_CFG_2_SET 0x64 48 #define CLK_CFG_2_CLR 0x68 49 #define CLK_CFG_3 0x70 50 #define CLK_CFG_3_SET 0x74 51 #define CLK_CFG_3_CLR 0x78 52 #define CLK_CFG_4 0x80 53 #define CLK_CFG_4_SET 0x84 54 #define CLK_CFG_4_CLR 0x88 55 #define CLK_CFG_5 0x90 56 #define CLK_CFG_5_SET 0x94 57 #define CLK_CFG_5_CLR 0x98 58 #define CLK_CFG_6 0xa0 59 #define CLK_CFG_6_SET 0xa4 60 #define CLK_CFG_6_CLR 0xa8 61 #define CLK_CFG_7 0xb0 62 #define CLK_CFG_7_SET 0xb4 63 #define CLK_CFG_7_CLR 0xb8 64 #define CLK_CFG_8 0xc0 65 #define CLK_CFG_8_SET 0xc4 66 #define CLK_CFG_8_CLR 0xc8 67 #define CLK_CFG_9 0xd0 68 #define CLK_CFG_9_SET 0xd4 69 #define CLK_CFG_9_CLR 0xd8 70 #define CLK_CFG_10 0xe0 71 #define CLK_CFG_10_SET 0xe4 72 #define CLK_CFG_10_CLR 0xe8 73 #define CLK_CFG_UPDATE 0x004 74 75 static const struct mtk_fixed_clk fixed_clks[] = { 76 FIXED_CLK(CLK_TOP_F_FRTC, "f_frtc_ck", "clk32k", 32768), 77 FIXED_CLK(CLK_TOP_CLK26M, "clk_26m_ck", "clk26m", 26000000), 78 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 466000000), 79 }; 80 81 static const struct mtk_fixed_factor top_divs[] = { 82 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), 83 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 84 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 85 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 86 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 87 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 88 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 89 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 90 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 91 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8), 92 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 93 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 94 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 95 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 96 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 97 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 98 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), 99 FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 2, 13), 100 FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4), 101 FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8), 102 FACTOR(CLK_TOP_USB20_192M_D16, 103 "usb20_192m_d16", "usb20_192m_ck", 1, 16), 104 FACTOR(CLK_TOP_USB20_192M_D32, 105 "usb20_192m_d32", "usb20_192m_ck", 1, 32), 106 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 107 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 108 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 109 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 110 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), 111 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), 112 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), 113 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32), 114 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 115 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 116 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 117 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 118 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2), 119 FACTOR(CLK_TOP_MPLL, "mpll_ck", "mpll", 1, 1), 120 FACTOR(CLK_TOP_DA_MPLL_104M_DIV, "mpll_104m_div", "mpll_ck", 1, 2), 121 FACTOR(CLK_TOP_DA_MPLL_52M_DIV, "mpll_52m_div", "mpll_ck", 1, 4), 122 FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1), 123 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 124 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2), 125 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 126 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 127 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), 128 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), 129 FACTOR(CLK_TOP_ULPOSC1, "ulposc1_ck", "ulposc1", 1, 1), 130 FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1_ck", 1, 2), 131 FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1_ck", 1, 4), 132 FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1_ck", 1, 8), 133 FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1_ck", 1, 16), 134 FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1_ck", 1, 32), 135 FACTOR(CLK_TOP_F_F26M, "f_f26m_ck", "clk_26m_ck", 1, 1), 136 FACTOR(CLK_TOP_AXI, "axi_ck", "axi_sel", 1, 1), 137 FACTOR(CLK_TOP_MM, "mm_ck", "mm_sel", 1, 1), 138 FACTOR(CLK_TOP_SCP, "scp_ck", "scp_sel", 1, 1), 139 FACTOR(CLK_TOP_MFG, "mfg_ck", "mfg_sel", 1, 1), 140 FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1), 141 FACTOR(CLK_TOP_SPI, "spi_ck", "spi_sel", 1, 1), 142 FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1), 143 FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 1, 1), 144 FACTOR(CLK_TOP_AUDIO, "audio_ck", "audio_sel", 1, 1), 145 FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1), 146 FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck", "aud_engen1_sel", 1, 1), 147 FACTOR(CLK_TOP_F_FDISP_PWM, "f_fdisp_pwm_ck", "disp_pwm_sel", 1, 1), 148 FACTOR(CLK_TOP_SSPM, "sspm_ck", "sspm_sel", 1, 1), 149 FACTOR(CLK_TOP_DXCC, "dxcc_ck", "dxcc_sel", 1, 1), 150 FACTOR(CLK_TOP_I2C, "i2c_ck", "i2c_sel", 1, 1), 151 FACTOR(CLK_TOP_F_FPWM, "f_fpwm_ck", "pwm_sel", 1, 1), 152 FACTOR(CLK_TOP_F_FSENINF, "f_fseninf_ck", "seninf_sel", 1, 1), 153 FACTOR(CLK_TOP_AES_FDE, "aes_fde_ck", "aes_fde_sel", 1, 1), 154 FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll2_d2", 1, 1), 155 FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL0, "arm_div_pll0", "syspll_d2", 1, 1), 156 FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL1, "arm_div_pll1", "syspll_ck", 1, 1), 157 FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL2, "arm_div_pll2", "univpll_d2", 1, 1), 158 FACTOR(CLK_TOP_DA_USB20_48M_DIV, 159 "usb20_48m_div", "usb20_192m_d4", 1, 1), 160 FACTOR(CLK_TOP_DA_UNIV_48M_DIV, "univ_48m_div", "usb20_192m_d4", 1, 1), 161 }; 162 163 static const char * const axi_parents[] = { 164 "clk26m", 165 "syspll_d7", 166 "syspll1_d4", 167 "syspll3_d2" 168 }; 169 170 static const char * const mem_parents[] = { 171 "clk26m", 172 "dmpll_ck", 173 "apll1_ck" 174 }; 175 176 static const char * const mm_parents[] = { 177 "clk26m", 178 "mmpll_ck", 179 "syspll1_d2", 180 "syspll_d5", 181 "syspll1_d4", 182 "univpll_d5", 183 "univpll1_d2", 184 "mmpll_d2" 185 }; 186 187 static const char * const scp_parents[] = { 188 "clk26m", 189 "syspll4_d2", 190 "univpll2_d2", 191 "syspll1_d2", 192 "univpll1_d2", 193 "syspll_d3", 194 "univpll_d3" 195 }; 196 197 static const char * const mfg_parents[] = { 198 "clk26m", 199 "mfgpll_ck", 200 "syspll_d3", 201 "univpll_d3" 202 }; 203 204 static const char * const atb_parents[] = { 205 "clk26m", 206 "syspll1_d4", 207 "syspll1_d2" 208 }; 209 210 static const char * const camtg_parents[] = { 211 "clk26m", 212 "usb20_192m_d8", 213 "univpll2_d8", 214 "usb20_192m_d4", 215 "univpll2_d32", 216 "usb20_192m_d16", 217 "usb20_192m_d32" 218 }; 219 220 static const char * const uart_parents[] = { 221 "clk26m", 222 "univpll2_d8" 223 }; 224 225 static const char * const spi_parents[] = { 226 "clk26m", 227 "syspll3_d2", 228 "syspll4_d2", 229 "syspll2_d4" 230 }; 231 232 static const char * const msdc5hclk_parents[] = { 233 "clk26m", 234 "syspll1_d2", 235 "univpll1_d4", 236 "syspll2_d2" 237 }; 238 239 static const char * const msdc50_0_parents[] = { 240 "clk26m", 241 "msdcpll_ck", 242 "syspll2_d2", 243 "syspll4_d2", 244 "univpll1_d2", 245 "syspll1_d2", 246 "univpll_d5", 247 "univpll1_d4" 248 }; 249 250 static const char * const msdc30_1_parents[] = { 251 "clk26m", 252 "msdcpll_d2", 253 "univpll2_d2", 254 "syspll2_d2", 255 "syspll1_d4", 256 "univpll1_d4", 257 "usb20_192m_d4", 258 "syspll2_d4" 259 }; 260 261 static const char * const audio_parents[] = { 262 "clk26m", 263 "syspll3_d4", 264 "syspll4_d4", 265 "syspll1_d16" 266 }; 267 268 static const char * const aud_intbus_parents[] = { 269 "clk26m", 270 "syspll1_d4", 271 "syspll4_d2" 272 }; 273 274 static const char * const aud_1_parents[] = { 275 "clk26m", 276 "apll1_ck" 277 }; 278 279 static const char * const aud_engen1_parents[] = { 280 "clk26m", 281 "apll1_d2", 282 "apll1_d4", 283 "apll1_d8" 284 }; 285 286 static const char * const disp_pwm_parents[] = { 287 "clk26m", 288 "univpll2_d4", 289 "ulposc1_d2", 290 "ulposc1_d8" 291 }; 292 293 static const char * const sspm_parents[] = { 294 "clk26m", 295 "syspll1_d2", 296 "syspll_d3" 297 }; 298 299 static const char * const dxcc_parents[] = { 300 "clk26m", 301 "syspll1_d2", 302 "syspll1_d4", 303 "syspll1_d8" 304 }; 305 306 static const char * const usb_top_parents[] = { 307 "clk26m", 308 "univpll3_d4" 309 }; 310 311 static const char * const spm_parents[] = { 312 "clk26m", 313 "syspll1_d8" 314 }; 315 316 static const char * const i2c_parents[] = { 317 "clk26m", 318 "univpll3_d4", 319 "univpll3_d2", 320 "syspll1_d8", 321 "syspll2_d8" 322 }; 323 324 static const char * const pwm_parents[] = { 325 "clk26m", 326 "univpll3_d4", 327 "syspll1_d8" 328 }; 329 330 static const char * const seninf_parents[] = { 331 "clk26m", 332 "univpll1_d4", 333 "univpll1_d2", 334 "univpll2_d2" 335 }; 336 337 static const char * const aes_fde_parents[] = { 338 "clk26m", 339 "msdcpll_ck", 340 "univpll_d3", 341 "univpll2_d2", 342 "univpll1_d2", 343 "syspll1_d2" 344 }; 345 346 static const char * const ulposc_parents[] = { 347 "clk26m", 348 "ulposc1_d4", 349 "ulposc1_d8", 350 "ulposc1_d16", 351 "ulposc1_d32" 352 }; 353 354 static const char * const camtm_parents[] = { 355 "clk26m", 356 "univpll1_d4", 357 "univpll1_d2", 358 "univpll2_d2" 359 }; 360 361 #define INVALID_UPDATE_REG 0xFFFFFFFF 362 #define INVALID_UPDATE_SHIFT -1 363 #define INVALID_MUX_GATE -1 364 365 static const struct mtk_mux top_muxes[] = { 366 /* CLK_CFG_0 */ 367 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 368 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 369 0, 2, 7, CLK_CFG_UPDATE, 0, 370 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 371 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 372 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 373 8, 2, 15, CLK_CFG_UPDATE, 1, 374 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 375 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0, 376 CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23, 377 CLK_CFG_UPDATE, 2), 378 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0, 379 CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, 380 CLK_CFG_UPDATE, 3), 381 /* CLK_CFG_1 */ 382 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1, 383 CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7, 384 CLK_CFG_UPDATE, 4), 385 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1, 386 CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15, 387 CLK_CFG_UPDATE, 5), 388 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", 389 camtg_parents, CLK_CFG_1, CLK_CFG_1_SET, 390 CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6), 391 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents, 392 CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 393 24, 3, 31, CLK_CFG_UPDATE, 7), 394 /* CLK_CFG_2 */ 395 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel", 396 camtg_parents, CLK_CFG_2, CLK_CFG_2_SET, 397 CLK_CFG_2_CLR, 0, 3, 7, CLK_CFG_UPDATE, 8), 398 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents, 399 CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 400 8, 3, 15, CLK_CFG_UPDATE, 9), 401 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 402 CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 1, 23, 403 CLK_CFG_UPDATE, 10), 404 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2, 405 CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31, 406 CLK_CFG_UPDATE, 11), 407 /* CLK_CFG_3 */ 408 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk", 409 msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET, 410 CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12, 0), 411 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 412 msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET, 413 CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13, 0), 414 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 415 msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET, 416 CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14, 0), 417 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 418 CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 419 24, 2, 31, CLK_CFG_UPDATE, 15), 420 /* CLK_CFG_4 */ 421 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 422 aud_intbus_parents, CLK_CFG_4, CLK_CFG_4_SET, 423 CLK_CFG_4_CLR, 0, 2, 7, CLK_CFG_UPDATE, 16), 424 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 425 CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 426 8, 1, 15, CLK_CFG_UPDATE, 17), 427 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 428 aud_engen1_parents, CLK_CFG_4, CLK_CFG_4_SET, 429 CLK_CFG_4_CLR, 16, 2, 23, CLK_CFG_UPDATE, 18), 430 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 431 disp_pwm_parents, CLK_CFG_4, CLK_CFG_4_SET, 432 CLK_CFG_4_CLR, 24, 2, 31, CLK_CFG_UPDATE, 19), 433 /* CLK_CFG_5 */ 434 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents, 435 CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7, 436 CLK_CFG_UPDATE, 20), 437 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents, 438 CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 2, 15, 439 CLK_CFG_UPDATE, 21), 440 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel", 441 usb_top_parents, CLK_CFG_5, CLK_CFG_5_SET, 442 CLK_CFG_5_CLR, 16, 1, 23, CLK_CFG_UPDATE, 22), 443 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, CLK_CFG_5, 444 CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31, 445 CLK_CFG_UPDATE, 23), 446 /* CLK_CFG_6 */ 447 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, CLK_CFG_6, 448 CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 3, 7, CLK_CFG_UPDATE, 449 24), 450 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6, 451 CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 2, 15, CLK_CFG_UPDATE, 452 25), 453 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents, 454 CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23, 455 CLK_CFG_UPDATE, 26), 456 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel", 457 aes_fde_parents, CLK_CFG_6, CLK_CFG_6_SET, 458 CLK_CFG_6_CLR, 24, 3, 31, CLK_CFG_UPDATE, 27), 459 /* CLK_CFG_7 */ 460 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel", 461 ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET, 462 CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28, 463 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 464 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents, 465 CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15, 466 CLK_CFG_UPDATE, 29), 467 }; 468 469 static const struct mtk_gate_regs top0_cg_regs = { 470 .set_ofs = 0x0, 471 .clr_ofs = 0x0, 472 .sta_ofs = 0x0, 473 }; 474 475 static const struct mtk_gate_regs top1_cg_regs = { 476 .set_ofs = 0x104, 477 .clr_ofs = 0x104, 478 .sta_ofs = 0x104, 479 }; 480 481 static const struct mtk_gate_regs top2_cg_regs = { 482 .set_ofs = 0x320, 483 .clr_ofs = 0x320, 484 .sta_ofs = 0x320, 485 }; 486 487 #define GATE_TOP0(_id, _name, _parent, _shift) \ 488 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 489 490 #define GATE_TOP1(_id, _name, _parent, _shift) \ 491 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 492 493 #define GATE_TOP2(_id, _name, _parent, _shift) \ 494 GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 495 496 static const struct mtk_gate top_clks[] = { 497 /* TOP0 */ 498 GATE_TOP0(CLK_TOP_MD_32K, "md_32k", "f_frtc_ck", 8), 499 GATE_TOP0(CLK_TOP_MD_26M, "md_26m", "f_f26m_ck", 9), 500 GATE_TOP0(CLK_TOP_MD2_32K, "md2_32k", "f_frtc_ck", 10), 501 GATE_TOP0(CLK_TOP_MD2_26M, "md2_26m", "f_f26m_ck", 11), 502 /* TOP1 */ 503 GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL0_EN, 504 "arm_div_pll0_en", "arm_div_pll0", 3), 505 GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN, 506 "arm_div_pll1_en", "arm_div_pll1", 4), 507 GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN, 508 "arm_div_pll2_en", "arm_div_pll2", 5), 509 GATE_TOP1(CLK_TOP_FMEM_OCC_DRC_EN, "drc_en", "univpll2_d2", 6), 510 GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_48m_div", 8), 511 GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "univ_48m_div", 9), 512 GATE_TOP1(CLK_TOP_F_UFS_MP_SAP_CFG_EN, "ufs_sap", "f_f26m_ck", 12), 513 GATE_TOP1(CLK_TOP_F_BIST2FPC_EN, "bist2fpc", "f_bist2fpc_ck", 16), 514 /* TOP2 */ 515 GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2), 516 GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3), 517 GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4), 518 GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5), 519 }; 520 521 static const struct mtk_gate_regs ifr2_cg_regs = { 522 .set_ofs = 0x80, 523 .clr_ofs = 0x84, 524 .sta_ofs = 0x90, 525 }; 526 527 static const struct mtk_gate_regs ifr3_cg_regs = { 528 .set_ofs = 0x88, 529 .clr_ofs = 0x8c, 530 .sta_ofs = 0x94, 531 }; 532 533 static const struct mtk_gate_regs ifr4_cg_regs = { 534 .set_ofs = 0xa4, 535 .clr_ofs = 0xa8, 536 .sta_ofs = 0xac, 537 }; 538 539 static const struct mtk_gate_regs ifr5_cg_regs = { 540 .set_ofs = 0xc0, 541 .clr_ofs = 0xc4, 542 .sta_ofs = 0xc8, 543 }; 544 545 #define GATE_IFR2(_id, _name, _parent, _shift) \ 546 GATE_MTK(_id, _name, _parent, &ifr2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 547 548 #define GATE_IFR3(_id, _name, _parent, _shift) \ 549 GATE_MTK(_id, _name, _parent, &ifr3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 550 551 #define GATE_IFR4(_id, _name, _parent, _shift) \ 552 GATE_MTK(_id, _name, _parent, &ifr4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 553 554 #define GATE_IFR5(_id, _name, _parent, _shift) \ 555 GATE_MTK(_id, _name, _parent, &ifr5_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 556 557 static const struct mtk_gate ifr_clks[] = { 558 /* INFRA_TOPAXI */ 559 /* INFRA PERI */ 560 /* INFRA mode 0 */ 561 GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_ck", 8), 562 GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_ck", 9), 563 GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_ck", 10), 564 GATE_IFR2(CLK_IFR_I2C_AP, "ifr_i2c_ap", "i2c_ck", 11), 565 GATE_IFR2(CLK_IFR_I2C_CCU, "ifr_i2c_ccu", "i2c_ck", 12), 566 GATE_IFR2(CLK_IFR_I2C_SSPM, "ifr_i2c_sspm", "i2c_ck", 13), 567 GATE_IFR2(CLK_IFR_I2C_RSV, "ifr_i2c_rsv", "i2c_ck", 14), 568 GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_ck", 15), 569 GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "f_fpwm_ck", 16), 570 GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "f_fpwm_ck", 17), 571 GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "f_fpwm_ck", 18), 572 GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "f_fpwm_ck", 19), 573 GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "f_fpwm_ck", 20), 574 GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "f_fpwm_ck", 21), 575 GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "f_fuart_ck", 22), 576 GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "f_fuart_ck", 23), 577 GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "f_f26m_ck", 27), 578 GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_dma", "axi_ck", 28), 579 GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_ck", 31), 580 /* INFRA mode 1 */ 581 GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_ck", 1), 582 GATE_IFR3(CLK_IFR_MSDC0, "ifr_msdc0", "msdc5hclk", 2), 583 GATE_IFR3(CLK_IFR_MSDC1, "ifr_msdc1", "axi_ck", 4), 584 GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_ck", 9), 585 GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "f_f26m_ck", 10), 586 GATE_IFR3(CLK_IFR_CCIF1_AP, "ifr_ccif1_ap", "axi_ck", 12), 587 GATE_IFR3(CLK_IFR_CCIF1_MD, "ifr_ccif1_md", "axi_ck", 13), 588 GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "f_f26m_ck", 14), 589 GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_ck", 18), 590 GATE_IFR3(CLK_IFR_DEVICE_APC, "ifr_dapc", "axi_ck", 20), 591 GATE_IFR3(CLK_IFR_CCIF_AP, "ifr_ccif_ap", "axi_ck", 23), 592 GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_ck", 25), 593 GATE_IFR3(CLK_IFR_CCIF_MD, "ifr_ccif_md", "axi_ck", 26), 594 /* INFRA mode 2 */ 595 GATE_IFR4(CLK_IFR_RG_PWM_FBCLK6, "ifr_pwmfb", "f_f26m_ck", 0), 596 GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "f_fdisp_pwm_ck", 2), 597 GATE_IFR4(CLK_IFR_CLDMA_BCLK, "ifr_cldmabclk", "axi_ck", 3), 598 GATE_IFR4(CLK_IFR_AUDIO_26M_BCLK, "ifr_audio26m", "f_f26m_ck", 4), 599 GATE_IFR4(CLK_IFR_SPI1, "ifr_spi1", "spi_ck", 6), 600 GATE_IFR4(CLK_IFR_I2C4, "ifr_i2c4", "i2c_ck", 7), 601 GATE_IFR4(CLK_IFR_SPI2, "ifr_spi2", "spi_ck", 9), 602 GATE_IFR4(CLK_IFR_SPI3, "ifr_spi3", "spi_ck", 10), 603 GATE_IFR4(CLK_IFR_I2C5, "ifr_i2c5", "i2c_ck", 18), 604 GATE_IFR4(CLK_IFR_I2C5_ARBITER, "ifr_i2c5a", "i2c_ck", 19), 605 GATE_IFR4(CLK_IFR_I2C5_IMM, "ifr_i2c5_imm", "i2c_ck", 20), 606 GATE_IFR4(CLK_IFR_I2C1_ARBITER, "ifr_i2c1a", "i2c_ck", 21), 607 GATE_IFR4(CLK_IFR_I2C1_IMM, "ifr_i2c1_imm", "i2c_ck", 22), 608 GATE_IFR4(CLK_IFR_I2C2_ARBITER, "ifr_i2c2a", "i2c_ck", 23), 609 GATE_IFR4(CLK_IFR_I2C2_IMM, "ifr_i2c2_imm", "i2c_ck", 24), 610 GATE_IFR4(CLK_IFR_SPI4, "ifr_spi4", "spi_ck", 25), 611 GATE_IFR4(CLK_IFR_SPI5, "ifr_spi5", "spi_ck", 26), 612 GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_ck", 27), 613 GATE_IFR4(CLK_IFR_FAES_FDE, "ifr_faes_fde_ck", "aes_fde_ck", 29), 614 /* INFRA mode 3 */ 615 GATE_IFR5(CLK_IFR_MSDC0_SELF, "ifr_msdc0sf", "msdc50_0_ck", 0), 616 GATE_IFR5(CLK_IFR_MSDC1_SELF, "ifr_msdc1sf", "msdc50_0_ck", 1), 617 GATE_IFR5(CLK_IFR_I2C6, "ifr_i2c6", "i2c_ck", 6), 618 GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_ck", 7), 619 GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_ck", 8), 620 GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_clk", "msdc50_0_ck", 9), 621 GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_clk", "msdc30_1_ck", 10), 622 GATE_IFR5(CLK_IFR_MCU_PM_BCLK, "ifr_mcu_pm_bclk", "axi_ck", 17), 623 GATE_IFR5(CLK_IFR_CCIF2_AP, "ifr_ccif2_ap", "axi_ck", 18), 624 GATE_IFR5(CLK_IFR_CCIF2_MD, "ifr_ccif2_md", "axi_ck", 19), 625 GATE_IFR5(CLK_IFR_CCIF3_AP, "ifr_ccif3_ap", "axi_ck", 20), 626 GATE_IFR5(CLK_IFR_CCIF3_MD, "ifr_ccif3_md", "axi_ck", 21), 627 }; 628 629 /* additional CCF control for mipi26M race condition(disp/camera) */ 630 static const struct mtk_gate_regs apmixed_cg_regs = { 631 .set_ofs = 0x14, 632 .clr_ofs = 0x14, 633 .sta_ofs = 0x14, 634 }; 635 636 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 637 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 638 639 static const struct mtk_gate apmixed_clks[] = { 640 /* AUDIO0 */ 641 GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", "f_f26m_ck", 642 4), 643 GATE_APMIXED(CLK_APMIXED_APPLL26M, "apmixed_appll26m", "f_f26m_ck", 644 5), 645 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck", 646 6), 647 GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", "f_f26m_ck", 648 7), 649 GATE_APMIXED(CLK_APMIXED_MMSYS_F26M, "apmixed_mmsys26m", "f_f26m_ck", 650 8), 651 GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", "f_f26m_ck", 652 9), 653 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck", 654 11), 655 GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", "f_f26m_ck", 656 13), 657 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 658 "f_f26m_ck", 14), 659 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck", 660 16), 661 }; 662 663 #define MT6765_PLL_FMAX (3800UL * MHZ) 664 #define MT6765_PLL_FMIN (1500UL * MHZ) 665 666 #define CON0_MT6765_RST_BAR BIT(23) 667 668 #define PLL_INFO_NULL (0xFF) 669 670 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 671 _pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\ 672 _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\ 673 .id = _id, \ 674 .name = _name, \ 675 .reg = _reg, \ 676 .pwr_reg = _pwr_reg, \ 677 .en_mask = _en_mask, \ 678 .flags = _flags, \ 679 .rst_bar_mask = CON0_MT6765_RST_BAR, \ 680 .fmax = MT6765_PLL_FMAX, \ 681 .fmin = MT6765_PLL_FMIN, \ 682 .pcwbits = _pcwbits, \ 683 .pcwibits = _pcwibits, \ 684 .pd_reg = _pd_reg, \ 685 .pd_shift = _pd_shift, \ 686 .tuner_reg = _tuner_reg, \ 687 .tuner_en_reg = _tuner_en_reg, \ 688 .tuner_en_bit = _tuner_en_bit, \ 689 .pcw_reg = _pcw_reg, \ 690 .pcw_shift = _pcw_shift, \ 691 .div_table = _div_table, \ 692 } 693 694 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 695 _pcwibits, _pd_reg, _pd_shift, _tuner_reg, \ 696 _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ 697 _pcw_shift) \ 698 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 699 _pcwbits, _pcwibits, _pd_reg, _pd_shift, \ 700 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 701 _pcw_reg, _pcw_shift, NULL) \ 702 703 static const struct mtk_pll_data plls[] = { 704 PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, 0, 705 PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0), 706 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0, 707 PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0), 708 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0, 709 PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0), 710 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, 0, 711 (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240, 712 0), 713 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, 0, 714 0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0), 715 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, 0, 716 0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0), 717 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, 0, 718 HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0), 719 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0, 720 0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0), 721 PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, 0, 722 0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0), 723 PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, 0, 724 PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0), 725 }; 726 727 static int clk_mt6765_apmixed_probe(struct platform_device *pdev) 728 { 729 struct clk_hw_onecell_data *clk_data; 730 int r; 731 struct device_node *node = pdev->dev.of_node; 732 void __iomem *base; 733 734 base = devm_platform_ioremap_resource(pdev, 0); 735 if (IS_ERR(base)) 736 return PTR_ERR(base); 737 738 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 739 if (!clk_data) 740 return -ENOMEM; 741 742 mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); 743 744 mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, 745 ARRAY_SIZE(apmixed_clks), clk_data); 746 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 747 748 if (r) 749 pr_err("%s(): could not register clock provider: %d\n", 750 __func__, r); 751 752 apmixed_base = base; 753 /* MPLL, CCIPLL, MAINPLL set HW mode, TDCLKSQ, CLKSQ1 */ 754 writel(readl(AP_PLL_CON3) & 0xFFFFFFE1, AP_PLL_CON3); 755 writel(readl(PLLON_CON0) & 0x01041041, PLLON_CON0); 756 writel(readl(PLLON_CON1) & 0x01041041, PLLON_CON1); 757 758 return r; 759 } 760 761 static int clk_mt6765_top_probe(struct platform_device *pdev) 762 { 763 int r; 764 struct device_node *node = pdev->dev.of_node; 765 void __iomem *base; 766 struct clk_hw_onecell_data *clk_data; 767 768 base = devm_platform_ioremap_resource(pdev, 0); 769 if (IS_ERR(base)) 770 return PTR_ERR(base); 771 772 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 773 if (!clk_data) 774 return -ENOMEM; 775 776 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), 777 clk_data); 778 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), 779 clk_data); 780 mtk_clk_register_muxes(&pdev->dev, top_muxes, 781 ARRAY_SIZE(top_muxes), node, 782 &mt6765_clk_lock, clk_data); 783 mtk_clk_register_gates(&pdev->dev, node, top_clks, 784 ARRAY_SIZE(top_clks), clk_data); 785 786 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 787 788 if (r) 789 pr_err("%s(): could not register clock provider: %d\n", 790 __func__, r); 791 792 cksys_base = base; 793 /* [4]:no need */ 794 writel(readl(CLK_SCP_CFG_0) | 0x3EF, CLK_SCP_CFG_0); 795 /*[1,2,3,8]: no need*/ 796 writel(readl(CLK_SCP_CFG_1) | 0x1, CLK_SCP_CFG_1); 797 798 return r; 799 } 800 801 static int clk_mt6765_ifr_probe(struct platform_device *pdev) 802 { 803 struct clk_hw_onecell_data *clk_data; 804 int r; 805 struct device_node *node = pdev->dev.of_node; 806 void __iomem *base; 807 808 base = devm_platform_ioremap_resource(pdev, 0); 809 if (IS_ERR(base)) 810 return PTR_ERR(base); 811 812 clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); 813 if (!clk_data) 814 return -ENOMEM; 815 816 mtk_clk_register_gates(&pdev->dev, node, ifr_clks, 817 ARRAY_SIZE(ifr_clks), clk_data); 818 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 819 820 if (r) 821 pr_err("%s(): could not register clock provider: %d\n", 822 __func__, r); 823 824 return r; 825 } 826 827 static const struct of_device_id of_match_clk_mt6765[] = { 828 { 829 .compatible = "mediatek,mt6765-apmixedsys", 830 .data = clk_mt6765_apmixed_probe, 831 }, { 832 .compatible = "mediatek,mt6765-topckgen", 833 .data = clk_mt6765_top_probe, 834 }, { 835 .compatible = "mediatek,mt6765-infracfg", 836 .data = clk_mt6765_ifr_probe, 837 }, { 838 /* sentinel */ 839 } 840 }; 841 MODULE_DEVICE_TABLE(of, of_match_clk_mt6765); 842 843 static int clk_mt6765_probe(struct platform_device *pdev) 844 { 845 int (*clk_probe)(struct platform_device *d); 846 int r; 847 848 clk_probe = of_device_get_match_data(&pdev->dev); 849 if (!clk_probe) 850 return -EINVAL; 851 852 r = clk_probe(pdev); 853 if (r) 854 dev_err(&pdev->dev, 855 "could not register clock provider: %s: %d\n", 856 pdev->name, r); 857 858 return r; 859 } 860 861 static struct platform_driver clk_mt6765_drv = { 862 .probe = clk_mt6765_probe, 863 .driver = { 864 .name = "clk-mt6765", 865 .of_match_table = of_match_clk_mt6765, 866 }, 867 }; 868 869 static int __init clk_mt6765_init(void) 870 { 871 return platform_driver_register(&clk_mt6765_drv); 872 } 873 874 arch_initcall(clk_mt6765_init); 875 876 MODULE_DESCRIPTION("MediaTek MT6765 main clocks driver"); 877 MODULE_LICENSE("GPL"); 878