1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/platform_device.h> 8 9 #include "clk-gate.h" 10 #include "clk-mtk.h" 11 12 #include <dt-bindings/clock/mediatek,mt6735-vencsys.h> 13 14 #define VENC_CG_CON 0x00 15 #define VENC_CG_SET 0x04 16 #define VENC_CG_CLR 0x08 17 18 static struct mtk_gate_regs venc_cg_regs = { 19 .set_ofs = VENC_CG_SET, 20 .clr_ofs = VENC_CG_CLR, 21 .sta_ofs = VENC_CG_CON, 22 }; 23 24 static const struct mtk_gate vencsys_gates[] = { 25 GATE_MTK(CLK_VENC_SMI_LARB3, "smi_larb3", "mm_sel", &venc_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv), 26 GATE_MTK(CLK_VENC_VENC, "venc", "mm_sel", &venc_cg_regs, 4, &mtk_clk_gate_ops_setclr_inv), 27 GATE_MTK(CLK_VENC_JPGENC, "jpgenc", "mm_sel", &venc_cg_regs, 8, &mtk_clk_gate_ops_setclr_inv), 28 GATE_MTK(CLK_VENC_JPGDEC, "jpgdec", "mm_sel", &venc_cg_regs, 12, &mtk_clk_gate_ops_setclr_inv), 29 }; 30 31 static const struct mtk_clk_desc vencsys_clks = { 32 .clks = vencsys_gates, 33 .num_clks = ARRAY_SIZE(vencsys_gates), 34 }; 35 36 static const struct of_device_id of_match_mt6735_vencsys[] = { 37 { .compatible = "mediatek,mt6735-vencsys", .data = &vencsys_clks }, 38 { /* sentinel */ } 39 }; 40 41 static struct platform_driver clk_mt6735_vencsys = { 42 .probe = mtk_clk_simple_probe, 43 .remove = mtk_clk_simple_remove, 44 .driver = { 45 .name = "clk-mt6735-vencsys", 46 .of_match_table = of_match_mt6735_vencsys, 47 }, 48 }; 49 module_platform_driver(clk_mt6735_vencsys); 50 51 MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); 52 MODULE_DESCRIPTION("Mediatek MT6735 vencsys clock driver"); 53 MODULE_LICENSE("GPL"); 54