1*0bd9b121SYassine Oudjana // SPDX-License-Identifier: GPL-2.0 2*0bd9b121SYassine Oudjana /* 3*0bd9b121SYassine Oudjana * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> 4*0bd9b121SYassine Oudjana */ 5*0bd9b121SYassine Oudjana 6*0bd9b121SYassine Oudjana #include <linux/clk-provider.h> 7*0bd9b121SYassine Oudjana #include <linux/platform_device.h> 8*0bd9b121SYassine Oudjana 9*0bd9b121SYassine Oudjana #include "clk-gate.h" 10*0bd9b121SYassine Oudjana #include "clk-mtk.h" 11*0bd9b121SYassine Oudjana 12*0bd9b121SYassine Oudjana #include <dt-bindings/clock/mediatek,mt6735-vencsys.h> 13*0bd9b121SYassine Oudjana 14*0bd9b121SYassine Oudjana #define VENC_CG_CON 0x00 15*0bd9b121SYassine Oudjana #define VENC_CG_SET 0x04 16*0bd9b121SYassine Oudjana #define VENC_CG_CLR 0x08 17*0bd9b121SYassine Oudjana 18*0bd9b121SYassine Oudjana static struct mtk_gate_regs venc_cg_regs = { 19*0bd9b121SYassine Oudjana .set_ofs = VENC_CG_SET, 20*0bd9b121SYassine Oudjana .clr_ofs = VENC_CG_CLR, 21*0bd9b121SYassine Oudjana .sta_ofs = VENC_CG_CON, 22*0bd9b121SYassine Oudjana }; 23*0bd9b121SYassine Oudjana 24*0bd9b121SYassine Oudjana static const struct mtk_gate vencsys_gates[] = { 25*0bd9b121SYassine Oudjana GATE_MTK(CLK_VENC_SMI_LARB3, "smi_larb3", "mm_sel", &venc_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv), 26*0bd9b121SYassine Oudjana GATE_MTK(CLK_VENC_VENC, "venc", "mm_sel", &venc_cg_regs, 4, &mtk_clk_gate_ops_setclr_inv), 27*0bd9b121SYassine Oudjana GATE_MTK(CLK_VENC_JPGENC, "jpgenc", "mm_sel", &venc_cg_regs, 8, &mtk_clk_gate_ops_setclr_inv), 28*0bd9b121SYassine Oudjana GATE_MTK(CLK_VENC_JPGDEC, "jpgdec", "mm_sel", &venc_cg_regs, 12, &mtk_clk_gate_ops_setclr_inv), 29*0bd9b121SYassine Oudjana }; 30*0bd9b121SYassine Oudjana 31*0bd9b121SYassine Oudjana static const struct mtk_clk_desc vencsys_clks = { 32*0bd9b121SYassine Oudjana .clks = vencsys_gates, 33*0bd9b121SYassine Oudjana .num_clks = ARRAY_SIZE(vencsys_gates), 34*0bd9b121SYassine Oudjana }; 35*0bd9b121SYassine Oudjana 36*0bd9b121SYassine Oudjana static const struct of_device_id of_match_mt6735_vencsys[] = { 37*0bd9b121SYassine Oudjana { .compatible = "mediatek,mt6735-vencsys", .data = &vencsys_clks }, 38*0bd9b121SYassine Oudjana { /* sentinel */ } 39*0bd9b121SYassine Oudjana }; 40*0bd9b121SYassine Oudjana 41*0bd9b121SYassine Oudjana static struct platform_driver clk_mt6735_vencsys = { 42*0bd9b121SYassine Oudjana .probe = mtk_clk_simple_probe, 43*0bd9b121SYassine Oudjana .remove = mtk_clk_simple_remove, 44*0bd9b121SYassine Oudjana .driver = { 45*0bd9b121SYassine Oudjana .name = "clk-mt6735-vencsys", 46*0bd9b121SYassine Oudjana .of_match_table = of_match_mt6735_vencsys, 47*0bd9b121SYassine Oudjana }, 48*0bd9b121SYassine Oudjana }; 49*0bd9b121SYassine Oudjana module_platform_driver(clk_mt6735_vencsys); 50*0bd9b121SYassine Oudjana 51*0bd9b121SYassine Oudjana MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); 52*0bd9b121SYassine Oudjana MODULE_DESCRIPTION("Mediatek MT6735 vencsys clock driver"); 53*0bd9b121SYassine Oudjana MODULE_LICENSE("GPL"); 54