1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 16 #include "clk-gate.h" 17 #include "clk-mtk.h" 18 19 #include <dt-bindings/clock/mt2712-clk.h> 20 21 static DEFINE_SPINLOCK(mt2712_clk_lock); 22 23 static const struct mtk_fixed_clk top_fixed_clks[] = { 24 FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000), 25 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000), 26 FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000), 27 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000), 28 FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000), 29 FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000), 30 FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000), 31 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000), 32 FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768), 33 FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747), 34 FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000), 35 FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000), 36 }; 37 38 static const struct mtk_fixed_factor top_divs[] = { 39 FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, 1), 40 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, 2), 41 FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, 1), 42 FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, 2), 43 FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, 3), 44 FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, 1), 45 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), 46 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2), 47 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 48 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 49 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 50 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 51 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, 3), 52 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 53 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 54 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, 5), 55 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 56 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 57 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, 7), 58 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 59 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 60 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1), 61 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 7), 62 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, 26), 63 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, 52), 64 FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, 104), 65 FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, 208), 66 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2), 67 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 68 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 69 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), 70 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 3), 71 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), 72 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), 73 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), 74 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 5), 75 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 76 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 77 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), 78 FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, 1), 79 FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, 1), 80 FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, 1), 81 FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, 1), 82 FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, 1), 83 FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, 1), 84 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 85 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 86 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), 87 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), 88 FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, 16), 89 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 90 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 91 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), 92 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), 93 FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, 16), 94 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1), 95 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, 2), 96 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, 4), 97 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, 8), 98 FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, 1), 99 FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, 2), 100 FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, 4), 101 FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, 8), 102 FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, 1), 103 FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, 1), 104 FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, 1), 105 FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, 2), 106 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 107 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2), 108 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), 109 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, 2), 110 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 1), 111 FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, 2), 112 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 113 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 114 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4), 115 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8), 116 FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, 1), 117 FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, 2), 118 FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, 4), 119 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 120 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2), 121 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4), 122 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), 123 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, 2), 124 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, 4), 125 FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, 4), 126 FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 3), 127 FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, 3), 128 }; 129 130 static const char * const axi_parents[] = { 131 "clk26m", 132 "syspll1_d2", 133 "syspll_d5", 134 "syspll1_d4", 135 "univpll_d5", 136 "univpll2_d2", 137 "msdcpll2_ck" 138 }; 139 140 static const char * const mem_parents[] = { 141 "clk26m", 142 "dmpll_ck" 143 }; 144 145 static const char * const mm_parents[] = { 146 "clk26m", 147 "vencpll_ck", 148 "syspll_d3", 149 "syspll1_d2", 150 "syspll_d5", 151 "syspll1_d4", 152 "univpll1_d2", 153 "univpll2_d2" 154 }; 155 156 static const char * const pwm_parents[] = { 157 "clk26m", 158 "univpll2_d4", 159 "univpll3_d2", 160 "univpll1_d4" 161 }; 162 163 static const char * const vdec_parents[] = { 164 "clk26m", 165 "vcodecpll_ck", 166 "tvdpll_429m", 167 "univpll_d3", 168 "vencpll_ck", 169 "syspll_d3", 170 "univpll1_d2", 171 "mmpll_d2", 172 "syspll3_d2", 173 "tvdpll_ck" 174 }; 175 176 static const char * const venc_parents[] = { 177 "clk26m", 178 "univpll1_d2", 179 "mmpll_d2", 180 "tvdpll_d2", 181 "syspll1_d2", 182 "univpll_d5", 183 "vcodecpll_d2", 184 "univpll2_d2", 185 "syspll3_d2" 186 }; 187 188 static const char * const mfg_parents[] = { 189 "clk26m", 190 "mmpll_ck", 191 "univpll_d3", 192 "clk26m", 193 "clk26m", 194 "clk26m", 195 "clk26m", 196 "clk26m", 197 "clk26m", 198 "syspll_d3", 199 "syspll1_d2", 200 "syspll_d5", 201 "univpll_d3", 202 "univpll1_d2", 203 "univpll_d5", 204 "univpll2_d2" 205 }; 206 207 static const char * const camtg_parents[] = { 208 "clk26m", 209 "univpll_d52", 210 "univpll_d208", 211 "univpll_d104", 212 "clk26m_d2", 213 "univpll_d26", 214 "univpll2_d8", 215 "syspll3_d4", 216 "syspll3_d2", 217 "univpll1_d4", 218 "univpll2_d2" 219 }; 220 221 static const char * const uart_parents[] = { 222 "clk26m", 223 "univpll2_d8" 224 }; 225 226 static const char * const spi_parents[] = { 227 "clk26m", 228 "univpll2_d4", 229 "univpll1_d4", 230 "univpll2_d2", 231 "univpll3_d2", 232 "univpll1_d8" 233 }; 234 235 static const char * const usb20_parents[] = { 236 "clk26m", 237 "univpll1_d8", 238 "univpll3_d4" 239 }; 240 241 static const char * const usb30_parents[] = { 242 "clk26m", 243 "univpll3_d2", 244 "univpll3_d4", 245 "univpll2_d4" 246 }; 247 248 static const char * const msdc50_0_h_parents[] = { 249 "clk26m", 250 "syspll1_d2", 251 "syspll2_d2", 252 "syspll4_d2", 253 "univpll_d5", 254 "univpll1_d4" 255 }; 256 257 static const char * const msdc50_0_parents[] = { 258 "clk26m", 259 "msdcpll_ck", 260 "msdcpll_d2", 261 "univpll1_d4", 262 "syspll2_d2", 263 "msdcpll_d4", 264 "vencpll_d2", 265 "univpll1_d2", 266 "msdcpll2_ck", 267 "msdcpll2_d2", 268 "msdcpll2_d4" 269 }; 270 271 static const char * const msdc30_1_parents[] = { 272 "clk26m", 273 "univpll2_d2", 274 "msdcpll_d2", 275 "univpll1_d4", 276 "syspll2_d2", 277 "univpll_d7", 278 "vencpll_d2" 279 }; 280 281 static const char * const msdc30_3_parents[] = { 282 "clk26m", 283 "msdcpll2_ck", 284 "msdcpll2_d2", 285 "univpll2_d2", 286 "msdcpll2_d4", 287 "univpll1_d4", 288 "syspll2_d2", 289 "syspll_d7", 290 "univpll_d7", 291 "vencpll_d2", 292 "msdcpll_ck", 293 "msdcpll_d2", 294 "msdcpll_d4" 295 }; 296 297 static const char * const audio_parents[] = { 298 "clk26m", 299 "syspll3_d4", 300 "syspll4_d4", 301 "syspll1_d16" 302 }; 303 304 static const char * const aud_intbus_parents[] = { 305 "clk26m", 306 "syspll1_d4", 307 "syspll4_d2", 308 "univpll3_d2", 309 "univpll2_d8", 310 "syspll3_d2", 311 "syspll3_d4" 312 }; 313 314 static const char * const pmicspi_parents[] = { 315 "clk26m", 316 "syspll1_d8", 317 "syspll3_d4", 318 "syspll1_d16", 319 "univpll3_d4", 320 "univpll_d26", 321 "syspll3_d4" 322 }; 323 324 static const char * const dpilvds1_parents[] = { 325 "clk26m", 326 "lvdspll2_ck", 327 "lvdspll2_d2", 328 "lvdspll2_d4", 329 "lvdspll2_d8", 330 "clkfpc" 331 }; 332 333 static const char * const atb_parents[] = { 334 "clk26m", 335 "syspll1_d2", 336 "univpll_d5", 337 "syspll_d5" 338 }; 339 340 static const char * const nr_parents[] = { 341 "clk26m", 342 "univpll1_d4", 343 "syspll2_d2", 344 "syspll1_d4", 345 "univpll1_d8", 346 "univpll3_d2", 347 "univpll2_d2", 348 "syspll_d5" 349 }; 350 351 static const char * const nfi2x_parents[] = { 352 "clk26m", 353 "syspll4_d4", 354 "univpll3_d4", 355 "univpll1_d8", 356 "syspll2_d4", 357 "univpll3_d2", 358 "syspll_d7", 359 "syspll2_d2", 360 "univpll2_d2", 361 "syspll_d5", 362 "syspll1_d2" 363 }; 364 365 static const char * const irda_parents[] = { 366 "clk26m", 367 "univpll2_d4", 368 "syspll2_d4", 369 "univpll2_d8" 370 }; 371 372 static const char * const cci400_parents[] = { 373 "clk26m", 374 "vencpll_ck", 375 "armca35pll_600m", 376 "armca35pll_400m", 377 "univpll_d2", 378 "syspll_d2", 379 "msdcpll_ck", 380 "univpll_d3" 381 }; 382 383 static const char * const aud_1_parents[] = { 384 "clk26m", 385 "apll1_ck", 386 "univpll2_d4", 387 "univpll2_d8" 388 }; 389 390 static const char * const aud_2_parents[] = { 391 "clk26m", 392 "apll2_ck", 393 "univpll2_d4", 394 "univpll2_d8" 395 }; 396 397 static const char * const mem_mfg_parents[] = { 398 "clk26m", 399 "mmpll_ck", 400 "univpll_d3" 401 }; 402 403 static const char * const axi_mfg_parents[] = { 404 "clk26m", 405 "axi_sel", 406 "univpll_d5" 407 }; 408 409 static const char * const scam_parents[] = { 410 "clk26m", 411 "syspll3_d2", 412 "univpll2_d4", 413 "syspll2_d4" 414 }; 415 416 static const char * const nfiecc_parents[] = { 417 "clk26m", 418 "nfi2x_sel", 419 "syspll_d7", 420 "syspll2_d2", 421 "univpll2_d2", 422 "univpll_d5", 423 "syspll1_d2" 424 }; 425 426 static const char * const pe2_mac_p0_parents[] = { 427 "clk26m", 428 "syspll1_d8", 429 "syspll4_d2", 430 "syspll2_d4", 431 "univpll2_d4", 432 "syspll3_d2" 433 }; 434 435 static const char * const dpilvds_parents[] = { 436 "clk26m", 437 "lvdspll_ck", 438 "lvdspll_d2", 439 "lvdspll_d4", 440 "lvdspll_d8", 441 "clkfpc" 442 }; 443 444 static const char * const hdcp_parents[] = { 445 "clk26m", 446 "syspll4_d2", 447 "syspll3_d4", 448 "univpll2_d4" 449 }; 450 451 static const char * const hdcp_24m_parents[] = { 452 "clk26m", 453 "univpll_d26", 454 "univpll_d52", 455 "univpll2_d8" 456 }; 457 458 static const char * const rtc_parents[] = { 459 "clkrtc_int", 460 "clkrtc_ext", 461 "clk26m", 462 "univpll3_d8" 463 }; 464 465 static const char * const spinor_parents[] = { 466 "clk26m", 467 "clk26m_d2", 468 "syspll4_d4", 469 "univpll2_d8", 470 "univpll3_d4", 471 "syspll4_d2", 472 "syspll2_d4", 473 "univpll2_d4", 474 "etherpll_125m", 475 "syspll1_d4" 476 }; 477 478 static const char * const apll_parents[] = { 479 "clk26m", 480 "apll1_ck", 481 "apll1_d2", 482 "apll1_d4", 483 "apll1_d8", 484 "apll1_d16", 485 "apll2_ck", 486 "apll2_d2", 487 "apll2_d4", 488 "apll2_d8", 489 "apll2_d16", 490 "clk26m", 491 "clk26m" 492 }; 493 494 static const char * const a1sys_hp_parents[] = { 495 "clk26m", 496 "apll1_ck", 497 "apll1_d2", 498 "apll1_d4", 499 "apll1_d8", 500 "apll1_d3" 501 }; 502 503 static const char * const a2sys_hp_parents[] = { 504 "clk26m", 505 "apll2_ck", 506 "apll2_d2", 507 "apll2_d4", 508 "apll2_d8", 509 "apll2_d3" 510 }; 511 512 static const char * const asm_l_parents[] = { 513 "clk26m", 514 "univpll2_d4", 515 "univpll2_d2", 516 "syspll_d5" 517 }; 518 519 static const char * const i2so1_parents[] = { 520 "clk26m", 521 "apll1_ck", 522 "apll2_ck" 523 }; 524 525 static const char * const ether_125m_parents[] = { 526 "clk26m", 527 "etherpll_125m", 528 "univpll3_d2" 529 }; 530 531 static const char * const ether_50m_parents[] = { 532 "clk26m", 533 "etherpll_50m", 534 "apll1_d3", 535 "univpll3_d4" 536 }; 537 538 static const char * const jpgdec_parents[] = { 539 "clk26m", 540 "univpll_d3", 541 "tvdpll_429m", 542 "vencpll_ck", 543 "syspll_d3", 544 "vcodecpll_ck", 545 "univpll1_d2", 546 "armca35pll_400m", 547 "tvdpll_429m_d2", 548 "tvdpll_429m_d4" 549 }; 550 551 static const char * const spislv_parents[] = { 552 "clk26m", 553 "univpll2_d4", 554 "univpll1_d4", 555 "univpll2_d2", 556 "univpll3_d2", 557 "univpll1_d8", 558 "univpll1_d2", 559 "univpll_d5" 560 }; 561 562 static const char * const ether_parents[] = { 563 "clk26m", 564 "etherpll_50m", 565 "univpll_d26" 566 }; 567 568 static const char * const di_parents[] = { 569 "clk26m", 570 "tvdpll_d2", 571 "tvdpll_d4", 572 "tvdpll_d8", 573 "vencpll_ck", 574 "vencpll_d2", 575 "cvbs", 576 "cvbs_d2" 577 }; 578 579 static const char * const tvd_parents[] = { 580 "clk26m", 581 "cvbs_d2", 582 "univpll2_d8" 583 }; 584 585 static const char * const i2c_parents[] = { 586 "clk26m", 587 "univpll_d26", 588 "univpll2_d4", 589 "univpll3_d2", 590 "univpll1_d4" 591 }; 592 593 static const char * const msdc0p_aes_parents[] = { 594 "clk26m", 595 "syspll_d2", 596 "univpll_d3", 597 "vcodecpll_ck" 598 }; 599 600 static const char * const cmsys_parents[] = { 601 "clk26m", 602 "univpll_d3", 603 "syspll_d3", 604 "syspll1_d2", 605 "syspll2_d2" 606 }; 607 608 static const char * const gcpu_parents[] = { 609 "clk26m", 610 "syspll_d3", 611 "syspll1_d2", 612 "univpll1_d2", 613 "univpll_d5", 614 "univpll3_d2", 615 "univpll_d3" 616 }; 617 618 static const char * const aud_apll1_parents[] = { 619 "apll1", 620 "clkaud_ext_i_1" 621 }; 622 623 static const char * const aud_apll2_parents[] = { 624 "apll2", 625 "clkaud_ext_i_2" 626 }; 627 628 static const char * const apll1_ref_parents[] = { 629 "clkaud_ext_i_2", 630 "clkaud_ext_i_1", 631 "clki2si0_mck_i", 632 "clki2si1_mck_i", 633 "clki2si2_mck_i", 634 "clktdmin_mclk_i", 635 "clki2si2_mck_i", 636 "clktdmin_mclk_i" 637 }; 638 639 static const char * const audull_vtx_parents[] = { 640 "d2a_ulclk_6p5m", 641 "clkaud_ext_i_0" 642 }; 643 644 static struct mtk_composite top_muxes[] = { 645 /* CLK_CFG_0 */ 646 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3, 647 7, CLK_IS_CRITICAL), 648 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1, 649 15, CLK_IS_CRITICAL), 650 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31), 651 /* CLK_CFG_1 */ 652 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7), 653 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15), 654 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23), 655 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 24, 4, 31), 656 /* CLK_CFG_2 */ 657 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x060, 0, 4, 7), 658 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15), 659 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 16, 3, 23), 660 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x060, 24, 2, 31), 661 /* CLK_CFG_3 */ 662 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x070, 0, 2, 7), 663 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 664 0x070, 8, 3, 15), 665 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 666 0x070, 16, 4, 23), 667 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 668 0x070, 24, 3, 31), 669 /* CLK_CFG_4 */ 670 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_parents, 671 0x080, 0, 3, 7), 672 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 673 0x080, 8, 4, 15), 674 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 675 0x080, 16, 2, 23), 676 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 677 0x080, 24, 3, 31), 678 /* CLK_CFG_5 */ 679 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x090, 0, 3, 7), 680 MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", dpilvds1_parents, 681 0x090, 8, 3, 15), 682 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x090, 16, 2, 23), 683 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_parents, 0x090, 24, 3, 31), 684 /* CLK_CFG_6 */ 685 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x0a0, 0, 4, 7), 686 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0a0, 8, 2, 15), 687 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x0a0, 16, 3, 23), 688 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0a0, 24, 2, 31), 689 /* CLK_CFG_7 */ 690 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x0b0, 0, 2, 7), 691 MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", mem_mfg_parents, 692 0x0b0, 8, 2, 15), 693 MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", axi_mfg_parents, 694 0x0b0, 16, 2, 23), 695 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x0b0, 24, 2, 31), 696 /* CLK_CFG_8 */ 697 MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 0x0c0, 0, 3, 7), 698 MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", pe2_mac_p0_parents, 699 0x0c0, 8, 3, 15), 700 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", pe2_mac_p0_parents, 701 0x0c0, 16, 3, 23), 702 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0c0, 24, 3, 31), 703 /* CLK_CFG_9 */ 704 MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", msdc50_0_h_parents, 705 0x0d0, 0, 3, 7), 706 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x0d0, 8, 2, 15), 707 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 708 0x0d0, 16, 2, 23), 709 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 710 0x0d0, 24, 2, 31, CLK_IS_CRITICAL), 711 /* CLK_CFG_10 */ 712 MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents, 0x500, 0, 4, 7), 713 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x500, 8, 4, 15), 714 MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", apll_parents, 0x500, 16, 4, 23), 715 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, 716 0x500, 24, 3, 31), 717 /* CLK_CFG_11 */ 718 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a2sys_hp_parents, 0x510, 0, 3, 7), 719 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, 0x510, 8, 2, 15), 720 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, 0x510, 16, 2, 23), 721 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, 0x510, 24, 2, 31), 722 /* CLK_CFG_12 */ 723 MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", i2so1_parents, 0x520, 0, 2, 7), 724 MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", i2so1_parents, 0x520, 8, 2, 15), 725 MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", i2so1_parents, 0x520, 16, 2, 23), 726 MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", i2so1_parents, 0x520, 24, 2, 31), 727 /* CLK_CFG_13 */ 728 MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", i2so1_parents, 0x530, 0, 2, 7), 729 MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", i2so1_parents, 0x530, 8, 2, 15), 730 MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", i2so1_parents, 0x530, 16, 2, 23), 731 MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", i2so1_parents, 0x530, 24, 2, 31), 732 /* CLK_CFG_14 */ 733 MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", ether_125m_parents, 734 0x540, 0, 2, 7), 735 MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", ether_50m_parents, 736 0x540, 8, 2, 15), 737 MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", jpgdec_parents, 0x540, 16, 4, 23), 738 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", spislv_parents, 0x540, 24, 3, 31), 739 /* CLK_CFG_15 */ 740 MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", ether_parents, 0x550, 0, 2, 7), 741 MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", camtg_parents, 0x550, 8, 4, 15), 742 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 0x550, 16, 3, 23), 743 MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", tvd_parents, 0x550, 24, 2, 31), 744 /* CLK_CFG_16 */ 745 MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x560, 0, 3, 7), 746 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", pwm_parents, 0x560, 8, 2, 15), 747 MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", msdc0p_aes_parents, 748 0x560, 16, 2, 23), 749 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 0x560, 24, 3, 31), 750 /* CLK_CFG_17 */ 751 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x570, 0, 3, 7), 752 /* CLK_AUDDIV_4 */ 753 MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", aud_apll1_parents, 0x134, 0, 1), 754 MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", aud_apll2_parents, 0x134, 1, 1), 755 MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", audull_vtx_parents, 756 0x134, 31, 1), 757 MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel", apll1_ref_parents, 0x134, 4, 3), 758 MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel", apll1_ref_parents, 0x134, 7, 3), 759 }; 760 761 static const char * const mcu_mp0_parents[] = { 762 "clk26m", 763 "armca35pll_ck", 764 "f_mp0_pll1_ck", 765 "f_mp0_pll2_ck" 766 }; 767 768 static const char * const mcu_mp2_parents[] = { 769 "clk26m", 770 "armca72pll_ck", 771 "f_big_pll1_ck", 772 "f_big_pll2_ck" 773 }; 774 775 static const char * const mcu_bus_parents[] = { 776 "clk26m", 777 "cci400_sel", 778 "f_bus_pll1_ck", 779 "f_bus_pll2_ck" 780 }; 781 782 static struct mtk_composite mcu_muxes[] = { 783 /* mp0_pll_divider_cfg */ 784 MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 785 9, 2, -1, CLK_IS_CRITICAL), 786 /* mp2_pll_divider_cfg */ 787 MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 788 9, 2, -1, CLK_IS_CRITICAL), 789 /* bus_pll_divider_cfg */ 790 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 791 9, 2, -1, CLK_IS_CRITICAL), 792 }; 793 794 static const struct mtk_clk_divider top_adj_divs[] = { 795 DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8), 796 DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8), 797 DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8), 798 DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8), 799 DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8), 800 DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8), 801 DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8), 802 DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8), 803 }; 804 805 static const struct mtk_gate_regs top0_cg_regs = { 806 .set_ofs = 0x120, 807 .clr_ofs = 0x120, 808 .sta_ofs = 0x120, 809 }; 810 811 static const struct mtk_gate_regs top1_cg_regs = { 812 .set_ofs = 0x424, 813 .clr_ofs = 0x424, 814 .sta_ofs = 0x424, 815 }; 816 817 #define GATE_TOP0(_id, _name, _parent, _shift) \ 818 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 819 820 #define GATE_TOP1(_id, _name, _parent, _shift) \ 821 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 822 823 static const struct mtk_gate top_clks[] = { 824 /* TOP0 */ 825 GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0), 826 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1), 827 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2), 828 GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3), 829 GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4), 830 GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5), 831 GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6), 832 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7), 833 /* TOP1 */ 834 GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0), 835 GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1), 836 GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2), 837 }; 838 839 static const struct mtk_gate_regs infra_cg_regs = { 840 .set_ofs = 0x40, 841 .clr_ofs = 0x44, 842 .sta_ofs = 0x48, 843 }; 844 845 #define GATE_INFRA(_id, _name, _parent, _shift) \ 846 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 847 848 static const struct mtk_gate infra_clks[] = { 849 GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), 850 GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), 851 GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), 852 GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), 853 GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24), 854 GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25), 855 GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26), 856 }; 857 858 static const struct mtk_gate_regs peri0_cg_regs = { 859 .set_ofs = 0x8, 860 .clr_ofs = 0x10, 861 .sta_ofs = 0x18, 862 }; 863 864 static const struct mtk_gate_regs peri1_cg_regs = { 865 .set_ofs = 0xc, 866 .clr_ofs = 0x14, 867 .sta_ofs = 0x1c, 868 }; 869 870 static const struct mtk_gate_regs peri2_cg_regs = { 871 .set_ofs = 0x42c, 872 .clr_ofs = 0x42c, 873 .sta_ofs = 0x42c, 874 }; 875 876 #define GATE_PERI0(_id, _name, _parent, _shift) \ 877 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 878 879 #define GATE_PERI1(_id, _name, _parent, _shift) \ 880 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 881 882 #define GATE_PERI2(_id, _name, _parent, _shift) \ 883 GATE_MTK(_id, _name, _parent, &peri2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 884 885 static const struct mtk_gate peri_clks[] = { 886 /* PERI0 */ 887 GATE_PERI0(CLK_PERI_NFI, "per_nfi", "axi_sel", 0), 888 GATE_PERI0(CLK_PERI_THERM, "per_therm", "axi_sel", 1), 889 GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", "pwm_sel", 2), 890 GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", "pwm_sel", 3), 891 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4), 892 GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", "pwm_sel", 5), 893 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6), 894 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7), 895 GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", "pwm_sel", 8), 896 GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", "pwm_sel", 9), 897 GATE_PERI0(CLK_PERI_PWM, "per_pwm", "pwm_sel", 10), 898 GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", "axi_sel", 13), 899 GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", "msdc50_0_sel", 14), 900 GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", "msdc30_1_sel", 15), 901 GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", "msdc30_2_sel", 16), 902 GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", "msdc30_3_sel", 17), 903 GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20), 904 GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21), 905 GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22), 906 GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23), 907 GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", "axi_sel", 24), 908 GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", "axi_sel", 25), 909 GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", "axi_sel", 26), 910 GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", "axi_sel", 27), 911 GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", "axi_sel", 28), 912 GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", "ltepll_fs26m", 29), 913 GATE_PERI0(CLK_PERI_SPI0, "per_spi0", "spi_sel", 30), 914 /* PERI1 */ 915 GATE_PERI1(CLK_PERI_SPI, "per_spi", "spinor_sel", 1), 916 GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", "axi_sel", 3), 917 GATE_PERI1(CLK_PERI_SPI2, "per_spi2", "spi_sel", 5), 918 GATE_PERI1(CLK_PERI_SPI3, "per_spi3", "spi_sel", 6), 919 GATE_PERI1(CLK_PERI_SPI5, "per_spi5", "spi_sel", 8), 920 GATE_PERI1(CLK_PERI_UART4, "per_uart4", "uart_sel", 9), 921 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", "uart_sel", 11), 922 GATE_PERI1(CLK_PERI_GMAC, "per_gmac", "uart_sel", 12), 923 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", "uart_sel", 14), 924 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", "uart_sel", 15), 925 GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", "uart_sel", 16), 926 /* PERI2 */ 927 GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", "msdc50_0_sel", 0), 928 GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", "msdc30_1_sel", 1), 929 GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", "msdc30_2_sel", 2), 930 GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", "msdc30_3_sel", 3), 931 GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", "msdc50_0_h_sel", 4), 932 GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", "msdc50_3_h_sel", 5), 933 GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q", "axi_sel", 6), 934 GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", "mem_sel", 7), 935 }; 936 937 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; 938 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 939 940 static const struct mtk_clk_rst_desc clk_rst_desc[] = { 941 /* infra */ 942 { 943 .version = MTK_RST_SIMPLE, 944 .rst_bank_ofs = infrasys_rst_ofs, 945 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 946 }, 947 /* peri */ 948 { 949 .version = MTK_RST_SIMPLE, 950 .rst_bank_ofs = pericfg_rst_ofs, 951 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 952 }, 953 }; 954 955 static const struct mtk_clk_desc topck_desc = { 956 .clks = top_clks, 957 .num_clks = ARRAY_SIZE(top_clks), 958 .fixed_clks = top_fixed_clks, 959 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 960 .factor_clks = top_divs, 961 .num_factor_clks = ARRAY_SIZE(top_divs), 962 .composite_clks = top_muxes, 963 .num_composite_clks = ARRAY_SIZE(top_muxes), 964 .divider_clks = top_adj_divs, 965 .num_divider_clks = ARRAY_SIZE(top_adj_divs), 966 .clk_lock = &mt2712_clk_lock, 967 }; 968 969 static const struct mtk_clk_desc mcu_desc = { 970 .composite_clks = mcu_muxes, 971 .num_composite_clks = ARRAY_SIZE(mcu_muxes), 972 .clk_lock = &mt2712_clk_lock, 973 }; 974 975 static const struct mtk_clk_desc infra_desc = { 976 .clks = infra_clks, 977 .num_clks = ARRAY_SIZE(infra_clks), 978 .rst_desc = &clk_rst_desc[0], 979 }; 980 981 static const struct mtk_clk_desc peri_desc = { 982 .clks = peri_clks, 983 .num_clks = ARRAY_SIZE(peri_clks), 984 .rst_desc = &clk_rst_desc[1], 985 }; 986 987 static const struct of_device_id of_match_clk_mt2712[] = { 988 { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, 989 { .compatible = "mediatek,mt2712-mcucfg", .data = &mcu_desc }, 990 { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, 991 { .compatible = "mediatek,mt2712-topckgen", .data = &topck_desc }, 992 { /* sentinel */ } 993 }; 994 MODULE_DEVICE_TABLE(of, of_match_clk_mt2712); 995 996 static struct platform_driver clk_mt2712_drv = { 997 .probe = mtk_clk_simple_probe, 998 .remove_new = mtk_clk_simple_remove, 999 .driver = { 1000 .name = "clk-mt2712", 1001 .of_match_table = of_match_clk_mt2712, 1002 }, 1003 }; 1004 module_platform_driver(clk_mt2712_drv); 1005 MODULE_LICENSE("GPL"); 1006