1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 13 #include "clk-gate.h" 14 #include "clk-mtk.h" 15 16 #include <dt-bindings/clock/mt2712-clk.h> 17 18 static DEFINE_SPINLOCK(mt2712_clk_lock); 19 20 static const struct mtk_fixed_clk top_fixed_clks[] = { 21 FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000), 22 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000), 23 FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000), 24 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000), 25 FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000), 26 FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000), 27 FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000), 28 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000), 29 FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768), 30 FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747), 31 FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000), 32 FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000), 33 }; 34 35 static const struct mtk_fixed_factor top_divs[] = { 36 FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, 1), 37 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, 2), 38 FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, 1), 39 FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, 2), 40 FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, 3), 41 FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, 1), 42 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), 43 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2), 44 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 45 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 46 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 47 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 48 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, 3), 49 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 50 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 51 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, 5), 52 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 53 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 54 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, 7), 55 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 56 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 57 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1), 58 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 7), 59 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, 26), 60 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, 52), 61 FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, 104), 62 FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, 208), 63 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2), 64 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 65 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 66 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), 67 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 3), 68 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), 69 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), 70 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), 71 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 5), 72 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 73 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 74 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), 75 FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, 1), 76 FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, 1), 77 FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, 1), 78 FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, 1), 79 FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, 1), 80 FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, 1), 81 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 82 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 83 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), 84 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), 85 FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, 16), 86 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 87 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 88 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), 89 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), 90 FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, 16), 91 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1), 92 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, 2), 93 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, 4), 94 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, 8), 95 FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, 1), 96 FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, 2), 97 FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, 4), 98 FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, 8), 99 FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, 1), 100 FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, 1), 101 FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, 1), 102 FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, 2), 103 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 104 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2), 105 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), 106 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, 2), 107 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 1), 108 FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, 2), 109 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 110 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 111 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4), 112 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8), 113 FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, 1), 114 FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, 2), 115 FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, 4), 116 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 117 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2), 118 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4), 119 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), 120 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, 2), 121 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, 4), 122 FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, 4), 123 FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 3), 124 FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, 3), 125 }; 126 127 static const char * const axi_parents[] = { 128 "clk26m", 129 "syspll1_d2", 130 "syspll_d5", 131 "syspll1_d4", 132 "univpll_d5", 133 "univpll2_d2", 134 "msdcpll2_ck" 135 }; 136 137 static const char * const mem_parents[] = { 138 "clk26m", 139 "dmpll_ck" 140 }; 141 142 static const char * const mm_parents[] = { 143 "clk26m", 144 "vencpll_ck", 145 "syspll_d3", 146 "syspll1_d2", 147 "syspll_d5", 148 "syspll1_d4", 149 "univpll1_d2", 150 "univpll2_d2" 151 }; 152 153 static const char * const pwm_parents[] = { 154 "clk26m", 155 "univpll2_d4", 156 "univpll3_d2", 157 "univpll1_d4" 158 }; 159 160 static const char * const vdec_parents[] = { 161 "clk26m", 162 "vcodecpll_ck", 163 "tvdpll_429m", 164 "univpll_d3", 165 "vencpll_ck", 166 "syspll_d3", 167 "univpll1_d2", 168 "mmpll_d2", 169 "syspll3_d2", 170 "tvdpll_ck" 171 }; 172 173 static const char * const venc_parents[] = { 174 "clk26m", 175 "univpll1_d2", 176 "mmpll_d2", 177 "tvdpll_d2", 178 "syspll1_d2", 179 "univpll_d5", 180 "vcodecpll_d2", 181 "univpll2_d2", 182 "syspll3_d2" 183 }; 184 185 static const char * const mfg_parents[] = { 186 "clk26m", 187 "mmpll_ck", 188 "univpll_d3", 189 "clk26m", 190 "clk26m", 191 "clk26m", 192 "clk26m", 193 "clk26m", 194 "clk26m", 195 "syspll_d3", 196 "syspll1_d2", 197 "syspll_d5", 198 "univpll_d3", 199 "univpll1_d2", 200 "univpll_d5", 201 "univpll2_d2" 202 }; 203 204 static const char * const camtg_parents[] = { 205 "clk26m", 206 "univpll_d52", 207 "univpll_d208", 208 "univpll_d104", 209 "clk26m_d2", 210 "univpll_d26", 211 "univpll2_d8", 212 "syspll3_d4", 213 "syspll3_d2", 214 "univpll1_d4", 215 "univpll2_d2" 216 }; 217 218 static const char * const uart_parents[] = { 219 "clk26m", 220 "univpll2_d8" 221 }; 222 223 static const char * const spi_parents[] = { 224 "clk26m", 225 "univpll2_d4", 226 "univpll1_d4", 227 "univpll2_d2", 228 "univpll3_d2", 229 "univpll1_d8" 230 }; 231 232 static const char * const usb20_parents[] = { 233 "clk26m", 234 "univpll1_d8", 235 "univpll3_d4" 236 }; 237 238 static const char * const usb30_parents[] = { 239 "clk26m", 240 "univpll3_d2", 241 "univpll3_d4", 242 "univpll2_d4" 243 }; 244 245 static const char * const msdc50_0_h_parents[] = { 246 "clk26m", 247 "syspll1_d2", 248 "syspll2_d2", 249 "syspll4_d2", 250 "univpll_d5", 251 "univpll1_d4" 252 }; 253 254 static const char * const msdc50_0_parents[] = { 255 "clk26m", 256 "msdcpll_ck", 257 "msdcpll_d2", 258 "univpll1_d4", 259 "syspll2_d2", 260 "msdcpll_d4", 261 "vencpll_d2", 262 "univpll1_d2", 263 "msdcpll2_ck", 264 "msdcpll2_d2", 265 "msdcpll2_d4" 266 }; 267 268 static const char * const msdc30_1_parents[] = { 269 "clk26m", 270 "univpll2_d2", 271 "msdcpll_d2", 272 "univpll1_d4", 273 "syspll2_d2", 274 "univpll_d7", 275 "vencpll_d2" 276 }; 277 278 static const char * const msdc30_3_parents[] = { 279 "clk26m", 280 "msdcpll2_ck", 281 "msdcpll2_d2", 282 "univpll2_d2", 283 "msdcpll2_d4", 284 "univpll1_d4", 285 "syspll2_d2", 286 "syspll_d7", 287 "univpll_d7", 288 "vencpll_d2", 289 "msdcpll_ck", 290 "msdcpll_d2", 291 "msdcpll_d4" 292 }; 293 294 static const char * const audio_parents[] = { 295 "clk26m", 296 "syspll3_d4", 297 "syspll4_d4", 298 "syspll1_d16" 299 }; 300 301 static const char * const aud_intbus_parents[] = { 302 "clk26m", 303 "syspll1_d4", 304 "syspll4_d2", 305 "univpll3_d2", 306 "univpll2_d8", 307 "syspll3_d2", 308 "syspll3_d4" 309 }; 310 311 static const char * const pmicspi_parents[] = { 312 "clk26m", 313 "syspll1_d8", 314 "syspll3_d4", 315 "syspll1_d16", 316 "univpll3_d4", 317 "univpll_d26", 318 "syspll3_d4" 319 }; 320 321 static const char * const dpilvds1_parents[] = { 322 "clk26m", 323 "lvdspll2_ck", 324 "lvdspll2_d2", 325 "lvdspll2_d4", 326 "lvdspll2_d8", 327 "clkfpc" 328 }; 329 330 static const char * const atb_parents[] = { 331 "clk26m", 332 "syspll1_d2", 333 "univpll_d5", 334 "syspll_d5" 335 }; 336 337 static const char * const nr_parents[] = { 338 "clk26m", 339 "univpll1_d4", 340 "syspll2_d2", 341 "syspll1_d4", 342 "univpll1_d8", 343 "univpll3_d2", 344 "univpll2_d2", 345 "syspll_d5" 346 }; 347 348 static const char * const nfi2x_parents[] = { 349 "clk26m", 350 "syspll4_d4", 351 "univpll3_d4", 352 "univpll1_d8", 353 "syspll2_d4", 354 "univpll3_d2", 355 "syspll_d7", 356 "syspll2_d2", 357 "univpll2_d2", 358 "syspll_d5", 359 "syspll1_d2" 360 }; 361 362 static const char * const irda_parents[] = { 363 "clk26m", 364 "univpll2_d4", 365 "syspll2_d4", 366 "univpll2_d8" 367 }; 368 369 static const char * const cci400_parents[] = { 370 "clk26m", 371 "vencpll_ck", 372 "armca35pll_600m", 373 "armca35pll_400m", 374 "univpll_d2", 375 "syspll_d2", 376 "msdcpll_ck", 377 "univpll_d3" 378 }; 379 380 static const char * const aud_1_parents[] = { 381 "clk26m", 382 "apll1_ck", 383 "univpll2_d4", 384 "univpll2_d8" 385 }; 386 387 static const char * const aud_2_parents[] = { 388 "clk26m", 389 "apll2_ck", 390 "univpll2_d4", 391 "univpll2_d8" 392 }; 393 394 static const char * const mem_mfg_parents[] = { 395 "clk26m", 396 "mmpll_ck", 397 "univpll_d3" 398 }; 399 400 static const char * const axi_mfg_parents[] = { 401 "clk26m", 402 "axi_sel", 403 "univpll_d5" 404 }; 405 406 static const char * const scam_parents[] = { 407 "clk26m", 408 "syspll3_d2", 409 "univpll2_d4", 410 "syspll2_d4" 411 }; 412 413 static const char * const nfiecc_parents[] = { 414 "clk26m", 415 "nfi2x_sel", 416 "syspll_d7", 417 "syspll2_d2", 418 "univpll2_d2", 419 "univpll_d5", 420 "syspll1_d2" 421 }; 422 423 static const char * const pe2_mac_p0_parents[] = { 424 "clk26m", 425 "syspll1_d8", 426 "syspll4_d2", 427 "syspll2_d4", 428 "univpll2_d4", 429 "syspll3_d2" 430 }; 431 432 static const char * const dpilvds_parents[] = { 433 "clk26m", 434 "lvdspll_ck", 435 "lvdspll_d2", 436 "lvdspll_d4", 437 "lvdspll_d8", 438 "clkfpc" 439 }; 440 441 static const char * const hdcp_parents[] = { 442 "clk26m", 443 "syspll4_d2", 444 "syspll3_d4", 445 "univpll2_d4" 446 }; 447 448 static const char * const hdcp_24m_parents[] = { 449 "clk26m", 450 "univpll_d26", 451 "univpll_d52", 452 "univpll2_d8" 453 }; 454 455 static const char * const rtc_parents[] = { 456 "clkrtc_int", 457 "clkrtc_ext", 458 "clk26m", 459 "univpll3_d8" 460 }; 461 462 static const char * const spinor_parents[] = { 463 "clk26m", 464 "clk26m_d2", 465 "syspll4_d4", 466 "univpll2_d8", 467 "univpll3_d4", 468 "syspll4_d2", 469 "syspll2_d4", 470 "univpll2_d4", 471 "etherpll_125m", 472 "syspll1_d4" 473 }; 474 475 static const char * const apll_parents[] = { 476 "clk26m", 477 "apll1_ck", 478 "apll1_d2", 479 "apll1_d4", 480 "apll1_d8", 481 "apll1_d16", 482 "apll2_ck", 483 "apll2_d2", 484 "apll2_d4", 485 "apll2_d8", 486 "apll2_d16", 487 "clk26m", 488 "clk26m" 489 }; 490 491 static const char * const a1sys_hp_parents[] = { 492 "clk26m", 493 "apll1_ck", 494 "apll1_d2", 495 "apll1_d4", 496 "apll1_d8", 497 "apll1_d3" 498 }; 499 500 static const char * const a2sys_hp_parents[] = { 501 "clk26m", 502 "apll2_ck", 503 "apll2_d2", 504 "apll2_d4", 505 "apll2_d8", 506 "apll2_d3" 507 }; 508 509 static const char * const asm_l_parents[] = { 510 "clk26m", 511 "univpll2_d4", 512 "univpll2_d2", 513 "syspll_d5" 514 }; 515 516 static const char * const i2so1_parents[] = { 517 "clk26m", 518 "apll1_ck", 519 "apll2_ck" 520 }; 521 522 static const char * const ether_125m_parents[] = { 523 "clk26m", 524 "etherpll_125m", 525 "univpll3_d2" 526 }; 527 528 static const char * const ether_50m_parents[] = { 529 "clk26m", 530 "etherpll_50m", 531 "apll1_d3", 532 "univpll3_d4" 533 }; 534 535 static const char * const jpgdec_parents[] = { 536 "clk26m", 537 "univpll_d3", 538 "tvdpll_429m", 539 "vencpll_ck", 540 "syspll_d3", 541 "vcodecpll_ck", 542 "univpll1_d2", 543 "armca35pll_400m", 544 "tvdpll_429m_d2", 545 "tvdpll_429m_d4" 546 }; 547 548 static const char * const spislv_parents[] = { 549 "clk26m", 550 "univpll2_d4", 551 "univpll1_d4", 552 "univpll2_d2", 553 "univpll3_d2", 554 "univpll1_d8", 555 "univpll1_d2", 556 "univpll_d5" 557 }; 558 559 static const char * const ether_parents[] = { 560 "clk26m", 561 "etherpll_50m", 562 "univpll_d26" 563 }; 564 565 static const char * const di_parents[] = { 566 "clk26m", 567 "tvdpll_d2", 568 "tvdpll_d4", 569 "tvdpll_d8", 570 "vencpll_ck", 571 "vencpll_d2", 572 "cvbs", 573 "cvbs_d2" 574 }; 575 576 static const char * const tvd_parents[] = { 577 "clk26m", 578 "cvbs_d2", 579 "univpll2_d8" 580 }; 581 582 static const char * const i2c_parents[] = { 583 "clk26m", 584 "univpll_d26", 585 "univpll2_d4", 586 "univpll3_d2", 587 "univpll1_d4" 588 }; 589 590 static const char * const msdc0p_aes_parents[] = { 591 "clk26m", 592 "syspll_d2", 593 "univpll_d3", 594 "vcodecpll_ck" 595 }; 596 597 static const char * const cmsys_parents[] = { 598 "clk26m", 599 "univpll_d3", 600 "syspll_d3", 601 "syspll1_d2", 602 "syspll2_d2" 603 }; 604 605 static const char * const gcpu_parents[] = { 606 "clk26m", 607 "syspll_d3", 608 "syspll1_d2", 609 "univpll1_d2", 610 "univpll_d5", 611 "univpll3_d2", 612 "univpll_d3" 613 }; 614 615 static const char * const aud_apll1_parents[] = { 616 "apll1", 617 "clkaud_ext_i_1" 618 }; 619 620 static const char * const aud_apll2_parents[] = { 621 "apll2", 622 "clkaud_ext_i_2" 623 }; 624 625 static const char * const apll1_ref_parents[] = { 626 "clkaud_ext_i_2", 627 "clkaud_ext_i_1", 628 "clki2si0_mck_i", 629 "clki2si1_mck_i", 630 "clki2si2_mck_i", 631 "clktdmin_mclk_i", 632 "clki2si2_mck_i", 633 "clktdmin_mclk_i" 634 }; 635 636 static const char * const audull_vtx_parents[] = { 637 "d2a_ulclk_6p5m", 638 "clkaud_ext_i_0" 639 }; 640 641 static struct mtk_composite top_muxes[] = { 642 /* CLK_CFG_0 */ 643 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3, 644 7, CLK_IS_CRITICAL), 645 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1, 646 15, CLK_IS_CRITICAL), 647 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31), 648 /* CLK_CFG_1 */ 649 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7), 650 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15), 651 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23), 652 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 24, 4, 31), 653 /* CLK_CFG_2 */ 654 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x060, 0, 4, 7), 655 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15), 656 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 16, 3, 23), 657 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x060, 24, 2, 31), 658 /* CLK_CFG_3 */ 659 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x070, 0, 2, 7), 660 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 661 0x070, 8, 3, 15), 662 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 663 0x070, 16, 4, 23), 664 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 665 0x070, 24, 3, 31), 666 /* CLK_CFG_4 */ 667 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_parents, 668 0x080, 0, 3, 7), 669 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 670 0x080, 8, 4, 15), 671 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 672 0x080, 16, 2, 23), 673 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 674 0x080, 24, 3, 31), 675 /* CLK_CFG_5 */ 676 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x090, 0, 3, 7), 677 MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", dpilvds1_parents, 678 0x090, 8, 3, 15), 679 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x090, 16, 2, 23), 680 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_parents, 0x090, 24, 3, 31), 681 /* CLK_CFG_6 */ 682 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x0a0, 0, 4, 7), 683 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0a0, 8, 2, 15), 684 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x0a0, 16, 3, 23), 685 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0a0, 24, 2, 31), 686 /* CLK_CFG_7 */ 687 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x0b0, 0, 2, 7), 688 MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", mem_mfg_parents, 689 0x0b0, 8, 2, 15), 690 MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", axi_mfg_parents, 691 0x0b0, 16, 2, 23), 692 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x0b0, 24, 2, 31), 693 /* CLK_CFG_8 */ 694 MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 0x0c0, 0, 3, 7), 695 MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", pe2_mac_p0_parents, 696 0x0c0, 8, 3, 15), 697 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", pe2_mac_p0_parents, 698 0x0c0, 16, 3, 23), 699 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0c0, 24, 3, 31), 700 /* CLK_CFG_9 */ 701 MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", msdc50_0_h_parents, 702 0x0d0, 0, 3, 7), 703 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x0d0, 8, 2, 15), 704 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 705 0x0d0, 16, 2, 23), 706 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 707 0x0d0, 24, 2, 31, CLK_IS_CRITICAL), 708 /* CLK_CFG_10 */ 709 MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents, 0x500, 0, 4, 7), 710 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x500, 8, 4, 15), 711 MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", apll_parents, 0x500, 16, 4, 23), 712 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, 713 0x500, 24, 3, 31), 714 /* CLK_CFG_11 */ 715 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a2sys_hp_parents, 0x510, 0, 3, 7), 716 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, 0x510, 8, 2, 15), 717 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, 0x510, 16, 2, 23), 718 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, 0x510, 24, 2, 31), 719 /* CLK_CFG_12 */ 720 MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", i2so1_parents, 0x520, 0, 2, 7), 721 MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", i2so1_parents, 0x520, 8, 2, 15), 722 MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", i2so1_parents, 0x520, 16, 2, 23), 723 MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", i2so1_parents, 0x520, 24, 2, 31), 724 /* CLK_CFG_13 */ 725 MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", i2so1_parents, 0x530, 0, 2, 7), 726 MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", i2so1_parents, 0x530, 8, 2, 15), 727 MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", i2so1_parents, 0x530, 16, 2, 23), 728 MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", i2so1_parents, 0x530, 24, 2, 31), 729 /* CLK_CFG_14 */ 730 MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", ether_125m_parents, 731 0x540, 0, 2, 7), 732 MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", ether_50m_parents, 733 0x540, 8, 2, 15), 734 MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", jpgdec_parents, 0x540, 16, 4, 23), 735 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", spislv_parents, 0x540, 24, 3, 31), 736 /* CLK_CFG_15 */ 737 MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", ether_parents, 0x550, 0, 2, 7), 738 MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", camtg_parents, 0x550, 8, 4, 15), 739 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 0x550, 16, 3, 23), 740 MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", tvd_parents, 0x550, 24, 2, 31), 741 /* CLK_CFG_16 */ 742 MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x560, 0, 3, 7), 743 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", pwm_parents, 0x560, 8, 2, 15), 744 MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", msdc0p_aes_parents, 745 0x560, 16, 2, 23), 746 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 0x560, 24, 3, 31), 747 /* CLK_CFG_17 */ 748 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x570, 0, 3, 7), 749 /* CLK_AUDDIV_4 */ 750 MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", aud_apll1_parents, 0x134, 0, 1), 751 MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", aud_apll2_parents, 0x134, 1, 1), 752 MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", audull_vtx_parents, 753 0x134, 31, 1), 754 MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel", apll1_ref_parents, 0x134, 4, 3), 755 MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel", apll1_ref_parents, 0x134, 7, 3), 756 }; 757 758 static const char * const mcu_mp0_parents[] = { 759 "clk26m", 760 "armca35pll_ck", 761 "f_mp0_pll1_ck", 762 "f_mp0_pll2_ck" 763 }; 764 765 static const char * const mcu_mp2_parents[] = { 766 "clk26m", 767 "armca72pll_ck", 768 "f_big_pll1_ck", 769 "f_big_pll2_ck" 770 }; 771 772 static const char * const mcu_bus_parents[] = { 773 "clk26m", 774 "cci400_sel", 775 "f_bus_pll1_ck", 776 "f_bus_pll2_ck" 777 }; 778 779 static struct mtk_composite mcu_muxes[] = { 780 /* mp0_pll_divider_cfg */ 781 MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 782 9, 2, -1, CLK_IS_CRITICAL), 783 /* mp2_pll_divider_cfg */ 784 MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 785 9, 2, -1, CLK_IS_CRITICAL), 786 /* bus_pll_divider_cfg */ 787 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 788 9, 2, -1, CLK_IS_CRITICAL), 789 }; 790 791 static const struct mtk_clk_divider top_adj_divs[] = { 792 DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8), 793 DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8), 794 DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8), 795 DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8), 796 DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8), 797 DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8), 798 DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8), 799 DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8), 800 }; 801 802 static const struct mtk_gate_regs top0_cg_regs = { 803 .set_ofs = 0x120, 804 .clr_ofs = 0x120, 805 .sta_ofs = 0x120, 806 }; 807 808 static const struct mtk_gate_regs top1_cg_regs = { 809 .set_ofs = 0x424, 810 .clr_ofs = 0x424, 811 .sta_ofs = 0x424, 812 }; 813 814 #define GATE_TOP0(_id, _name, _parent, _shift) \ 815 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 816 817 #define GATE_TOP1(_id, _name, _parent, _shift) \ 818 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 819 820 static const struct mtk_gate top_clks[] = { 821 /* TOP0 */ 822 GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0), 823 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1), 824 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2), 825 GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3), 826 GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4), 827 GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5), 828 GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6), 829 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7), 830 /* TOP1 */ 831 GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0), 832 GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1), 833 GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2), 834 }; 835 836 static const struct mtk_gate_regs infra_cg_regs = { 837 .set_ofs = 0x40, 838 .clr_ofs = 0x44, 839 .sta_ofs = 0x48, 840 }; 841 842 #define GATE_INFRA(_id, _name, _parent, _shift) \ 843 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 844 845 static const struct mtk_gate infra_clks[] = { 846 GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), 847 GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), 848 GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), 849 GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), 850 GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24), 851 GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25), 852 GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26), 853 }; 854 855 static const struct mtk_gate_regs peri0_cg_regs = { 856 .set_ofs = 0x8, 857 .clr_ofs = 0x10, 858 .sta_ofs = 0x18, 859 }; 860 861 static const struct mtk_gate_regs peri1_cg_regs = { 862 .set_ofs = 0xc, 863 .clr_ofs = 0x14, 864 .sta_ofs = 0x1c, 865 }; 866 867 static const struct mtk_gate_regs peri2_cg_regs = { 868 .set_ofs = 0x42c, 869 .clr_ofs = 0x42c, 870 .sta_ofs = 0x42c, 871 }; 872 873 #define GATE_PERI0(_id, _name, _parent, _shift) \ 874 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 875 876 #define GATE_PERI1(_id, _name, _parent, _shift) \ 877 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 878 879 #define GATE_PERI2(_id, _name, _parent, _shift) \ 880 GATE_MTK(_id, _name, _parent, &peri2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 881 882 static const struct mtk_gate peri_clks[] = { 883 /* PERI0 */ 884 GATE_PERI0(CLK_PERI_NFI, "per_nfi", "axi_sel", 0), 885 GATE_PERI0(CLK_PERI_THERM, "per_therm", "axi_sel", 1), 886 GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", "pwm_sel", 2), 887 GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", "pwm_sel", 3), 888 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4), 889 GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", "pwm_sel", 5), 890 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6), 891 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7), 892 GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", "pwm_sel", 8), 893 GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", "pwm_sel", 9), 894 GATE_PERI0(CLK_PERI_PWM, "per_pwm", "pwm_sel", 10), 895 GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", "axi_sel", 13), 896 GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", "msdc50_0_sel", 14), 897 GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", "msdc30_1_sel", 15), 898 GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", "msdc30_2_sel", 16), 899 GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", "msdc30_3_sel", 17), 900 GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20), 901 GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21), 902 GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22), 903 GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23), 904 GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", "axi_sel", 24), 905 GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", "axi_sel", 25), 906 GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", "axi_sel", 26), 907 GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", "axi_sel", 27), 908 GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", "axi_sel", 28), 909 GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", "ltepll_fs26m", 29), 910 GATE_PERI0(CLK_PERI_SPI0, "per_spi0", "spi_sel", 30), 911 /* PERI1 */ 912 GATE_PERI1(CLK_PERI_SPI, "per_spi", "spinor_sel", 1), 913 GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", "axi_sel", 3), 914 GATE_PERI1(CLK_PERI_SPI2, "per_spi2", "spi_sel", 5), 915 GATE_PERI1(CLK_PERI_SPI3, "per_spi3", "spi_sel", 6), 916 GATE_PERI1(CLK_PERI_SPI5, "per_spi5", "spi_sel", 8), 917 GATE_PERI1(CLK_PERI_UART4, "per_uart4", "uart_sel", 9), 918 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", "uart_sel", 11), 919 GATE_PERI1(CLK_PERI_GMAC, "per_gmac", "uart_sel", 12), 920 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", "uart_sel", 14), 921 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", "uart_sel", 15), 922 GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", "uart_sel", 16), 923 /* PERI2 */ 924 GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", "msdc50_0_sel", 0), 925 GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", "msdc30_1_sel", 1), 926 GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", "msdc30_2_sel", 2), 927 GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", "msdc30_3_sel", 3), 928 GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", "msdc50_0_h_sel", 4), 929 GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", "msdc50_3_h_sel", 5), 930 GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q", "axi_sel", 6), 931 GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", "mem_sel", 7), 932 }; 933 934 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; 935 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 936 937 static const struct mtk_clk_rst_desc clk_rst_desc[] = { 938 /* infra */ 939 { 940 .version = MTK_RST_SIMPLE, 941 .rst_bank_ofs = infrasys_rst_ofs, 942 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 943 }, 944 /* peri */ 945 { 946 .version = MTK_RST_SIMPLE, 947 .rst_bank_ofs = pericfg_rst_ofs, 948 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 949 }, 950 }; 951 952 static const struct mtk_clk_desc topck_desc = { 953 .clks = top_clks, 954 .num_clks = ARRAY_SIZE(top_clks), 955 .fixed_clks = top_fixed_clks, 956 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 957 .factor_clks = top_divs, 958 .num_factor_clks = ARRAY_SIZE(top_divs), 959 .composite_clks = top_muxes, 960 .num_composite_clks = ARRAY_SIZE(top_muxes), 961 .divider_clks = top_adj_divs, 962 .num_divider_clks = ARRAY_SIZE(top_adj_divs), 963 .clk_lock = &mt2712_clk_lock, 964 }; 965 966 static const struct mtk_clk_desc mcu_desc = { 967 .composite_clks = mcu_muxes, 968 .num_composite_clks = ARRAY_SIZE(mcu_muxes), 969 .clk_lock = &mt2712_clk_lock, 970 }; 971 972 static const struct mtk_clk_desc infra_desc = { 973 .clks = infra_clks, 974 .num_clks = ARRAY_SIZE(infra_clks), 975 .rst_desc = &clk_rst_desc[0], 976 }; 977 978 static const struct mtk_clk_desc peri_desc = { 979 .clks = peri_clks, 980 .num_clks = ARRAY_SIZE(peri_clks), 981 .rst_desc = &clk_rst_desc[1], 982 }; 983 984 static const struct of_device_id of_match_clk_mt2712[] = { 985 { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, 986 { .compatible = "mediatek,mt2712-mcucfg", .data = &mcu_desc }, 987 { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, 988 { .compatible = "mediatek,mt2712-topckgen", .data = &topck_desc }, 989 { /* sentinel */ } 990 }; 991 MODULE_DEVICE_TABLE(of, of_match_clk_mt2712); 992 993 static struct platform_driver clk_mt2712_drv = { 994 .probe = mtk_clk_simple_probe, 995 .remove = mtk_clk_simple_remove, 996 .driver = { 997 .name = "clk-mt2712", 998 .of_match_table = of_match_clk_mt2712, 999 }, 1000 }; 1001 module_platform_driver(clk_mt2712_drv); 1002 1003 MODULE_DESCRIPTION("MediaTek MT2712 main clocks driver"); 1004 MODULE_LICENSE("GPL"); 1005