1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/platform_device.h> 9 10 #include "clk-mtk.h" 11 #include "clk-gate.h" 12 13 #include <dt-bindings/clock/mt2712-clk.h> 14 15 static const struct mtk_gate_regs venc_cg_regs = { 16 .set_ofs = 0x4, 17 .clr_ofs = 0x8, 18 .sta_ofs = 0x0, 19 }; 20 21 #define GATE_VENC(_id, _name, _parent, _shift) { \ 22 .id = _id, \ 23 .name = _name, \ 24 .parent_name = _parent, \ 25 .regs = &venc_cg_regs, \ 26 .shift = _shift, \ 27 .ops = &mtk_clk_gate_ops_setclr_inv, \ 28 } 29 30 static const struct mtk_gate venc_clks[] = { 31 GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0), 32 GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4), 33 GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12), 34 }; 35 36 static int clk_mt2712_venc_probe(struct platform_device *pdev) 37 { 38 struct clk_hw_onecell_data *clk_data; 39 int r; 40 struct device_node *node = pdev->dev.of_node; 41 42 clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK); 43 44 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), 45 clk_data); 46 47 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 48 49 if (r != 0) 50 pr_err("%s(): could not register clock provider: %d\n", 51 __func__, r); 52 53 return r; 54 } 55 56 static const struct of_device_id of_match_clk_mt2712_venc[] = { 57 { .compatible = "mediatek,mt2712-vencsys", }, 58 {} 59 }; 60 61 static struct platform_driver clk_mt2712_venc_drv = { 62 .probe = clk_mt2712_venc_probe, 63 .driver = { 64 .name = "clk-mt2712-venc", 65 .of_match_table = of_match_clk_mt2712_venc, 66 }, 67 }; 68 69 builtin_platform_driver(clk_mt2712_venc_drv); 70