1 /* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Weiyi Lu <weiyi.lu@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/clk-provider.h> 16 #include <linux/platform_device.h> 17 18 #include "clk-mtk.h" 19 #include "clk-gate.h" 20 21 #include <dt-bindings/clock/mt2712-clk.h> 22 23 static const struct mtk_gate_regs bdp_cg_regs = { 24 .set_ofs = 0x100, 25 .clr_ofs = 0x100, 26 .sta_ofs = 0x100, 27 }; 28 29 #define GATE_BDP(_id, _name, _parent, _shift) { \ 30 .id = _id, \ 31 .name = _name, \ 32 .parent_name = _parent, \ 33 .regs = &bdp_cg_regs, \ 34 .shift = _shift, \ 35 .ops = &mtk_clk_gate_ops_no_setclr, \ 36 } 37 38 static const struct mtk_gate bdp_clks[] = { 39 GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0), 40 GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1), 41 GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2), 42 GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3), 43 GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4), 44 GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5), 45 GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9), 46 GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10), 47 GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11), 48 GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12), 49 GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13), 50 GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14), 51 GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15), 52 GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16), 53 GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17), 54 GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18), 55 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19), 56 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20), 57 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21), 58 GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22), 59 GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23), 60 GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24), 61 GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25), 62 GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26), 63 GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27), 64 GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28), 65 GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29), 66 GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30), 67 }; 68 69 static int clk_mt2712_bdp_probe(struct platform_device *pdev) 70 { 71 struct clk_onecell_data *clk_data; 72 int r; 73 struct device_node *node = pdev->dev.of_node; 74 75 clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK); 76 77 mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks), 78 clk_data); 79 80 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 81 82 if (r != 0) 83 pr_err("%s(): could not register clock provider: %d\n", 84 __func__, r); 85 86 return r; 87 } 88 89 static const struct of_device_id of_match_clk_mt2712_bdp[] = { 90 { .compatible = "mediatek,mt2712-bdpsys", }, 91 {} 92 }; 93 94 static struct platform_driver clk_mt2712_bdp_drv = { 95 .probe = clk_mt2712_bdp_probe, 96 .driver = { 97 .name = "clk-mt2712-bdp", 98 .of_match_table = of_match_clk_mt2712_bdp, 99 }, 100 }; 101 102 builtin_platform_driver(clk_mt2712_bdp_drv); 103