1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Shunli Wang <shunli.wang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/clk-provider.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 21 #include "clk-mtk.h" 22 #include "clk-gate.h" 23 #include "clk-cpumux.h" 24 25 #include <dt-bindings/clock/mt2701-clk.h> 26 27 /* 28 * For some clocks, we don't care what their actual rates are. And these 29 * clocks may change their rate on different products or different scenarios. 30 * So we model these clocks' rate as 0, to denote it's not an actual rate. 31 */ 32 #define DUMMY_RATE 0 33 34 static DEFINE_SPINLOCK(mt2701_clk_lock); 35 36 static const struct mtk_fixed_clk top_fixed_clks[] = { 37 FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m", 38 108 * MHZ), 39 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m", 40 400 * MHZ), 41 FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m", 42 295750000), 43 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m", 44 340 * MHZ), 45 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m", 46 340 * MHZ), 47 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m", 48 340 * MHZ), 49 FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m", 50 300 * MHZ), 51 FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m", 52 27 * MHZ), 53 FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m", 54 416 * MHZ), 55 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m", 56 143 * MHZ), 57 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m", 58 27 * MHZ), 59 FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m", 60 DUMMY_RATE), 61 FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m", 62 DUMMY_RATE), 63 FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m", 64 DUMMY_RATE), 65 }; 66 67 static const struct mtk_fixed_factor top_fixed_divs[] = { 68 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), 69 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 70 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 71 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 72 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 73 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 74 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 75 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 76 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 77 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 78 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 79 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8), 80 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 81 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 82 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 83 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 84 85 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1), 86 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 87 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 88 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 89 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 90 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26), 91 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52), 92 FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108), 93 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26), 94 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 95 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 96 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), 97 FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1), 98 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), 99 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), 100 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), 101 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16), 102 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32), 103 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 104 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 105 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), 106 107 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 108 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 109 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 110 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 111 112 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 113 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 114 115 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2), 116 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4), 117 FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1), 118 119 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 120 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), 121 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 122 123 FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1), 124 FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1), 125 FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2), 126 127 FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1), 128 FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2), 129 FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4), 130 131 FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1), 132 FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2), 133 FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3), 134 135 FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1), 136 137 FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1), 138 FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4), 139 FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8), 140 FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16), 141 FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24), 142 143 FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3), 144 FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3), 145 FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3), 146 FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1), 147 FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1), 148 FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8), 149 FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793), 150 FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1), 151 }; 152 153 static const char * const axi_parents[] = { 154 "clk26m", 155 "syspll1_d2", 156 "syspll_d5", 157 "syspll1_d4", 158 "univpll_d5", 159 "univpll2_d2", 160 "mmpll_d2", 161 "dmpll_d2" 162 }; 163 164 static const char * const mem_parents[] = { 165 "clk26m", 166 "dmpll_ck" 167 }; 168 169 static const char * const ddrphycfg_parents[] = { 170 "clk26m", 171 "syspll1_d8" 172 }; 173 174 static const char * const mm_parents[] = { 175 "clk26m", 176 "vencpll_ck", 177 "syspll1_d2", 178 "syspll1_d4", 179 "univpll_d5", 180 "univpll1_d2", 181 "univpll2_d2", 182 "dmpll_ck" 183 }; 184 185 static const char * const pwm_parents[] = { 186 "clk26m", 187 "univpll2_d4", 188 "univpll3_d2", 189 "univpll1_d4", 190 }; 191 192 static const char * const vdec_parents[] = { 193 "clk26m", 194 "vdecpll_ck", 195 "syspll_d5", 196 "syspll1_d4", 197 "univpll_d5", 198 "univpll2_d2", 199 "vencpll_ck", 200 "msdcpll_d2", 201 "mmpll_d2" 202 }; 203 204 static const char * const mfg_parents[] = { 205 "clk26m", 206 "mmpll_ck", 207 "dmpll_x2_ck", 208 "msdcpll_ck", 209 "clk26m", 210 "syspll_d3", 211 "univpll_d3", 212 "univpll1_d2" 213 }; 214 215 static const char * const camtg_parents[] = { 216 "clk26m", 217 "univpll_d26", 218 "univpll2_d2", 219 "syspll3_d2", 220 "syspll3_d4", 221 "msdcpll_d2", 222 "mmpll_d2" 223 }; 224 225 static const char * const uart_parents[] = { 226 "clk26m", 227 "univpll2_d8" 228 }; 229 230 static const char * const spi_parents[] = { 231 "clk26m", 232 "syspll3_d2", 233 "syspll4_d2", 234 "univpll2_d4", 235 "univpll1_d8" 236 }; 237 238 static const char * const usb20_parents[] = { 239 "clk26m", 240 "univpll1_d8", 241 "univpll3_d4" 242 }; 243 244 static const char * const msdc30_parents[] = { 245 "clk26m", 246 "msdcpll_d2", 247 "syspll2_d2", 248 "syspll1_d4", 249 "univpll1_d4", 250 "univpll2_d4" 251 }; 252 253 static const char * const audio_parents[] = { 254 "clk26m", 255 "syspll1_d16" 256 }; 257 258 static const char * const aud_intbus_parents[] = { 259 "clk26m", 260 "syspll1_d4", 261 "syspll3_d2", 262 "syspll4_d2", 263 "univpll3_d2", 264 "univpll2_d4" 265 }; 266 267 static const char * const pmicspi_parents[] = { 268 "clk26m", 269 "syspll1_d8", 270 "syspll2_d4", 271 "syspll4_d2", 272 "syspll3_d4", 273 "syspll2_d8", 274 "syspll1_d16", 275 "univpll3_d4", 276 "univpll_d26", 277 "dmpll_d2", 278 "dmpll_d4" 279 }; 280 281 static const char * const scp_parents[] = { 282 "clk26m", 283 "syspll1_d8", 284 "dmpll_d2", 285 "dmpll_d4" 286 }; 287 288 static const char * const dpi0_parents[] = { 289 "clk26m", 290 "mipipll", 291 "mipipll_d2", 292 "mipipll_d4", 293 "clk26m", 294 "tvdpll_ck", 295 "tvdpll_d2", 296 "tvdpll_d4" 297 }; 298 299 static const char * const dpi1_parents[] = { 300 "clk26m", 301 "tvdpll_ck", 302 "tvdpll_d2", 303 "tvdpll_d4" 304 }; 305 306 static const char * const tve_parents[] = { 307 "clk26m", 308 "mipipll", 309 "mipipll_d2", 310 "mipipll_d4", 311 "clk26m", 312 "tvdpll_ck", 313 "tvdpll_d2", 314 "tvdpll_d4" 315 }; 316 317 static const char * const hdmi_parents[] = { 318 "clk26m", 319 "hdmipll_ck", 320 "hdmipll_d2", 321 "hdmipll_d3" 322 }; 323 324 static const char * const apll_parents[] = { 325 "clk26m", 326 "audpll", 327 "audpll_d4", 328 "audpll_d8", 329 "audpll_d16", 330 "audpll_d24", 331 "clk26m", 332 "clk26m" 333 }; 334 335 static const char * const rtc_parents[] = { 336 "32k_internal", 337 "32k_external", 338 "clk26m", 339 "univpll3_d8" 340 }; 341 342 static const char * const nfi2x_parents[] = { 343 "clk26m", 344 "syspll2_d2", 345 "syspll_d7", 346 "univpll3_d2", 347 "syspll2_d4", 348 "univpll3_d4", 349 "syspll4_d4", 350 "clk26m" 351 }; 352 353 static const char * const emmc_hclk_parents[] = { 354 "clk26m", 355 "syspll1_d2", 356 "syspll1_d4", 357 "syspll2_d2" 358 }; 359 360 static const char * const flash_parents[] = { 361 "clk26m_d8", 362 "clk26m", 363 "syspll2_d8", 364 "syspll3_d4", 365 "univpll3_d4", 366 "syspll4_d2", 367 "syspll2_d4", 368 "univpll2_d4" 369 }; 370 371 static const char * const di_parents[] = { 372 "clk26m", 373 "tvd2pll_ck", 374 "tvd2pll_d2", 375 "clk26m" 376 }; 377 378 static const char * const nr_osd_parents[] = { 379 "clk26m", 380 "vencpll_ck", 381 "syspll1_d2", 382 "syspll1_d4", 383 "univpll_d5", 384 "univpll1_d2", 385 "univpll2_d2", 386 "dmpll_ck" 387 }; 388 389 static const char * const hdmirx_bist_parents[] = { 390 "clk26m", 391 "syspll_d3", 392 "clk26m", 393 "syspll1_d16", 394 "syspll4_d2", 395 "syspll1_d4", 396 "vencpll_ck", 397 "clk26m" 398 }; 399 400 static const char * const intdir_parents[] = { 401 "clk26m", 402 "mmpll_ck", 403 "syspll_d2", 404 "univpll_d2" 405 }; 406 407 static const char * const asm_parents[] = { 408 "clk26m", 409 "univpll2_d4", 410 "univpll2_d2", 411 "syspll_d5" 412 }; 413 414 static const char * const ms_card_parents[] = { 415 "clk26m", 416 "univpll3_d8", 417 "syspll4_d4" 418 }; 419 420 static const char * const ethif_parents[] = { 421 "clk26m", 422 "syspll1_d2", 423 "syspll_d5", 424 "syspll1_d4", 425 "univpll_d5", 426 "univpll1_d2", 427 "dmpll_ck", 428 "dmpll_d2" 429 }; 430 431 static const char * const hdmirx_parents[] = { 432 "clk26m", 433 "univpll_d52" 434 }; 435 436 static const char * const cmsys_parents[] = { 437 "clk26m", 438 "syspll1_d2", 439 "univpll1_d2", 440 "univpll_d5", 441 "syspll_d5", 442 "syspll2_d2", 443 "syspll1_d4", 444 "syspll3_d2", 445 "syspll2_d4", 446 "syspll1_d8", 447 "clk26m", 448 "clk26m", 449 "clk26m", 450 "clk26m", 451 "clk26m" 452 }; 453 454 static const char * const clk_8bdac_parents[] = { 455 "32k_internal", 456 "8bdac_ck", 457 "clk26m", 458 "clk26m" 459 }; 460 461 static const char * const aud2dvd_parents[] = { 462 "a1sys_hp_ck", 463 "a2sys_hp_ck" 464 }; 465 466 static const char * const padmclk_parents[] = { 467 "clk26m", 468 "univpll_d26", 469 "univpll_d52", 470 "univpll_d108", 471 "univpll2_d8", 472 "univpll2_d16", 473 "univpll2_d32" 474 }; 475 476 static const char * const aud_mux_parents[] = { 477 "clk26m", 478 "aud1pll_98m_ck", 479 "aud2pll_90m_ck", 480 "hadds2pll_98m", 481 "audio_ext1_ck", 482 "audio_ext2_ck" 483 }; 484 485 static const char * const aud_src_parents[] = { 486 "aud_mux1_sel", 487 "aud_mux2_sel" 488 }; 489 490 static const char * const cpu_parents[] = { 491 "clk26m", 492 "armpll", 493 "mainpll", 494 "mmpll" 495 }; 496 497 static const struct mtk_composite cpu_muxes[] __initconst = { 498 MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2), 499 }; 500 501 static const struct mtk_composite top_muxes[] = { 502 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 503 0x0040, 0, 3, 7, CLK_IS_CRITICAL), 504 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 505 0x0040, 8, 1, 15, CLK_IS_CRITICAL), 506 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", 507 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL), 508 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 509 0x0040, 24, 3, 31), 510 511 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 512 0x0050, 0, 2, 7), 513 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 514 0x0050, 8, 4, 15), 515 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 516 0x0050, 16, 3, 23), 517 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 518 0x0050, 24, 3, 31), 519 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 520 0x0060, 0, 1, 7), 521 522 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents, 523 0x0060, 8, 3, 15), 524 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 525 0x0060, 16, 2, 23), 526 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 527 0x0060, 24, 3, 31), 528 529 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 530 0x0070, 0, 3, 7), 531 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 532 0x0070, 8, 3, 15), 533 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents, 534 0x0070, 16, 1, 23), 535 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 536 0x0070, 24, 3, 31), 537 538 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 539 0x0080, 0, 4, 7), 540 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 541 0x0080, 8, 2, 15), 542 MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 543 0x0080, 16, 3, 23), 544 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 545 0x0080, 24, 2, 31), 546 547 MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 548 0x0090, 0, 3, 7), 549 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 550 0x0090, 8, 2, 15), 551 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 552 0x0090, 16, 3, 23), 553 554 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 555 0x00A0, 0, 2, 7, CLK_IS_CRITICAL), 556 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 557 0x00A0, 8, 3, 15), 558 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents, 559 0x00A0, 24, 2, 31), 560 561 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 562 0x00B0, 0, 3, 7), 563 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 564 0x00B0, 8, 2, 15), 565 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents, 566 0x00B0, 16, 3, 23), 567 MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents, 568 0x00B0, 24, 3, 31), 569 570 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel", 571 hdmirx_bist_parents, 0x00C0, 0, 3, 7), 572 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 573 0x00C0, 8, 2, 15), 574 MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents, 575 0x00C0, 16, 2, 23), 576 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents, 577 0x00C0, 24, 3, 31), 578 579 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents, 580 0x00D0, 0, 2, 7), 581 MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents, 582 0x00D0, 16, 2, 23), 583 MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents, 584 0x00D0, 24, 3, 31), 585 586 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents, 587 0x00E0, 0, 1, 7), 588 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 589 0x00E0, 8, 3, 15), 590 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 591 0x00E0, 16, 4, 23), 592 593 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents, 594 0x00E0, 24, 3, 31), 595 MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents, 596 0x00F0, 0, 3, 7), 597 MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents, 598 0x00F0, 8, 2, 15), 599 MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents, 600 0x00F0, 16, 1, 23), 601 602 MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents, 603 0x0100, 0, 3), 604 605 MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents, 606 0x012c, 0, 3), 607 MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents, 608 0x012c, 3, 3), 609 MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents, 610 0x012c, 6, 3), 611 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents, 612 0x012c, 15, 1, 23), 613 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents, 614 0x012c, 16, 1, 24), 615 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents, 616 0x012c, 17, 1, 25), 617 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents, 618 0x012c, 18, 1, 26), 619 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents, 620 0x012c, 19, 1, 27), 621 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents, 622 0x012c, 20, 1, 28), 623 }; 624 625 static const struct mtk_clk_divider top_adj_divs[] = { 626 DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1", 627 0x0120, 0, 8), 628 DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2", 629 0x0120, 8, 8), 630 DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel", 631 0x0120, 16, 8), 632 DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel", 633 0x0120, 24, 8), 634 DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel", 635 0x0124, 0, 8), 636 DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel", 637 0x0124, 8, 8), 638 DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel", 639 0x0124, 16, 8), 640 DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel", 641 0x0124, 24, 8), 642 DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel", 643 0x0128, 0, 8), 644 DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel", 645 0x0128, 8, 8), 646 }; 647 648 static const struct mtk_gate_regs top_aud_cg_regs = { 649 .sta_ofs = 0x012C, 650 }; 651 652 #define GATE_TOP_AUD(_id, _name, _parent, _shift) { \ 653 .id = _id, \ 654 .name = _name, \ 655 .parent_name = _parent, \ 656 .regs = &top_aud_cg_regs, \ 657 .shift = _shift, \ 658 .ops = &mtk_clk_gate_ops_no_setclr, \ 659 } 660 661 static const struct mtk_gate top_clks[] = { 662 GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div", 663 21), 664 GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div", 665 22), 666 GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div", 667 23), 668 GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div", 669 24), 670 GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div", 671 25), 672 GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div", 673 26), 674 GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div", 675 27), 676 GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 677 28), 678 }; 679 680 static int mtk_topckgen_init(struct platform_device *pdev) 681 { 682 struct clk_onecell_data *clk_data; 683 void __iomem *base; 684 struct device_node *node = pdev->dev.of_node; 685 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 686 687 base = devm_ioremap_resource(&pdev->dev, res); 688 if (IS_ERR(base)) 689 return PTR_ERR(base); 690 691 clk_data = mtk_alloc_clk_data(CLK_TOP_NR); 692 693 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 694 clk_data); 695 696 mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), 697 clk_data); 698 699 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), 700 base, &mt2701_clk_lock, clk_data); 701 702 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 703 base, &mt2701_clk_lock, clk_data); 704 705 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 706 clk_data); 707 708 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 709 } 710 711 static const struct mtk_gate_regs infra_cg_regs = { 712 .set_ofs = 0x0040, 713 .clr_ofs = 0x0044, 714 .sta_ofs = 0x0048, 715 }; 716 717 #define GATE_ICG(_id, _name, _parent, _shift) { \ 718 .id = _id, \ 719 .name = _name, \ 720 .parent_name = _parent, \ 721 .regs = &infra_cg_regs, \ 722 .shift = _shift, \ 723 .ops = &mtk_clk_gate_ops_setclr, \ 724 } 725 726 static const struct mtk_gate infra_clks[] = { 727 GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0), 728 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1), 729 GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2), 730 GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4), 731 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5), 732 GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6), 733 GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7), 734 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), 735 GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12), 736 GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13), 737 GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14), 738 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15), 739 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), 740 GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18), 741 GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19), 742 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), 743 GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23), 744 GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24), 745 }; 746 747 static const struct mtk_fixed_factor infra_fixed_divs[] = { 748 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), 749 }; 750 751 static struct clk_onecell_data *infra_clk_data; 752 753 static void mtk_infrasys_init_early(struct device_node *node) 754 { 755 int r, i; 756 757 if (!infra_clk_data) { 758 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 759 760 for (i = 0; i < CLK_INFRA_NR; i++) 761 infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); 762 } 763 764 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 765 infra_clk_data); 766 767 mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), 768 infra_clk_data); 769 770 r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); 771 if (r) 772 pr_err("%s(): could not register clock provider: %d\n", 773 __func__, r); 774 } 775 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg", 776 mtk_infrasys_init_early); 777 778 static int mtk_infrasys_init(struct platform_device *pdev) 779 { 780 int r, i; 781 struct device_node *node = pdev->dev.of_node; 782 783 if (!infra_clk_data) { 784 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 785 } else { 786 for (i = 0; i < CLK_INFRA_NR; i++) { 787 if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) 788 infra_clk_data->clks[i] = ERR_PTR(-ENOENT); 789 } 790 } 791 792 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 793 infra_clk_data); 794 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 795 infra_clk_data); 796 797 r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); 798 if (r) 799 return r; 800 801 mtk_register_reset_controller(node, 2, 0x30); 802 803 return 0; 804 } 805 806 static const struct mtk_gate_regs peri0_cg_regs = { 807 .set_ofs = 0x0008, 808 .clr_ofs = 0x0010, 809 .sta_ofs = 0x0018, 810 }; 811 812 static const struct mtk_gate_regs peri1_cg_regs = { 813 .set_ofs = 0x000c, 814 .clr_ofs = 0x0014, 815 .sta_ofs = 0x001c, 816 }; 817 818 #define GATE_PERI0(_id, _name, _parent, _shift) { \ 819 .id = _id, \ 820 .name = _name, \ 821 .parent_name = _parent, \ 822 .regs = &peri0_cg_regs, \ 823 .shift = _shift, \ 824 .ops = &mtk_clk_gate_ops_setclr, \ 825 } 826 827 #define GATE_PERI1(_id, _name, _parent, _shift) { \ 828 .id = _id, \ 829 .name = _name, \ 830 .parent_name = _parent, \ 831 .regs = &peri1_cg_regs, \ 832 .shift = _shift, \ 833 .ops = &mtk_clk_gate_ops_setclr, \ 834 } 835 836 static const struct mtk_gate peri_clks[] = { 837 GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31), 838 GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30), 839 GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29), 840 GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28), 841 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27), 842 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26), 843 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25), 844 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24), 845 GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23), 846 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22), 847 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21), 848 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20), 849 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19), 850 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18), 851 GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17), 852 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16), 853 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15), 854 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14), 855 GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13), 856 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), 857 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), 858 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), 859 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), 860 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8), 861 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7), 862 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6), 863 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5), 864 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4), 865 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3), 866 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2), 867 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), 868 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0), 869 870 GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11), 871 GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10), 872 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9), 873 GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8), 874 GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7), 875 GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6), 876 GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5), 877 GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4), 878 GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3), 879 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2), 880 GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1), 881 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0), 882 }; 883 884 static const char * const uart_ck_sel_parents[] = { 885 "clk26m", 886 "uart_sel", 887 }; 888 889 static const struct mtk_composite peri_muxs[] = { 890 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 891 0x40c, 0, 1), 892 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 893 0x40c, 1, 1), 894 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 895 0x40c, 2, 1), 896 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 897 0x40c, 3, 1), 898 }; 899 900 static int mtk_pericfg_init(struct platform_device *pdev) 901 { 902 struct clk_onecell_data *clk_data; 903 void __iomem *base; 904 int r; 905 struct device_node *node = pdev->dev.of_node; 906 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 907 908 base = devm_ioremap_resource(&pdev->dev, res); 909 if (IS_ERR(base)) 910 return PTR_ERR(base); 911 912 clk_data = mtk_alloc_clk_data(CLK_PERI_NR); 913 914 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), 915 clk_data); 916 917 mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, 918 &mt2701_clk_lock, clk_data); 919 920 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 921 if (r) 922 return r; 923 924 mtk_register_reset_controller(node, 2, 0x0); 925 926 return 0; 927 } 928 929 #define MT8590_PLL_FMAX (2000 * MHZ) 930 #define CON0_MT8590_RST_BAR BIT(27) 931 932 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 933 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ 934 .id = _id, \ 935 .name = _name, \ 936 .reg = _reg, \ 937 .pwr_reg = _pwr_reg, \ 938 .en_mask = _en_mask, \ 939 .flags = _flags, \ 940 .rst_bar_mask = CON0_MT8590_RST_BAR, \ 941 .fmax = MT8590_PLL_FMAX, \ 942 .pcwbits = _pcwbits, \ 943 .pd_reg = _pd_reg, \ 944 .pd_shift = _pd_shift, \ 945 .tuner_reg = _tuner_reg, \ 946 .pcw_reg = _pcw_reg, \ 947 .pcw_shift = _pcw_shift, \ 948 } 949 950 static const struct mtk_pll_data apmixed_plls[] = { 951 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001, 952 PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0), 953 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001, 954 HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0), 955 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001, 956 HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14), 957 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0, 958 21, 0x230, 4, 0x0, 0x234, 0), 959 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 960 21, 0x240, 4, 0x0, 0x244, 0), 961 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0, 962 21, 0x250, 4, 0x0, 0x254, 0), 963 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0, 964 31, 0x270, 4, 0x0, 0x274, 0), 965 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0, 966 31, 0x280, 4, 0x0, 0x284, 0), 967 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0, 968 31, 0x290, 4, 0x0, 0x294, 0), 969 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0, 970 31, 0x2a0, 4, 0x0, 0x2a4, 0), 971 PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0, 972 31, 0x2b0, 4, 0x0, 0x2b4, 0), 973 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0, 974 31, 0x2c0, 4, 0x0, 0x2c4, 0), 975 PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0, 976 21, 0x2d0, 4, 0x0, 0x2d4, 0), 977 }; 978 979 static int mtk_apmixedsys_init(struct platform_device *pdev) 980 { 981 struct clk_onecell_data *clk_data; 982 struct device_node *node = pdev->dev.of_node; 983 984 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR); 985 if (!clk_data) 986 return -ENOMEM; 987 988 mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls), 989 clk_data); 990 991 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 992 } 993 994 static const struct of_device_id of_match_clk_mt2701[] = { 995 { 996 .compatible = "mediatek,mt2701-topckgen", 997 .data = mtk_topckgen_init, 998 }, { 999 .compatible = "mediatek,mt2701-infracfg", 1000 .data = mtk_infrasys_init, 1001 }, { 1002 .compatible = "mediatek,mt2701-pericfg", 1003 .data = mtk_pericfg_init, 1004 }, { 1005 .compatible = "mediatek,mt2701-apmixedsys", 1006 .data = mtk_apmixedsys_init, 1007 }, { 1008 /* sentinel */ 1009 } 1010 }; 1011 1012 static int clk_mt2701_probe(struct platform_device *pdev) 1013 { 1014 int (*clk_init)(struct platform_device *); 1015 int r; 1016 1017 clk_init = of_device_get_match_data(&pdev->dev); 1018 if (!clk_init) 1019 return -EINVAL; 1020 1021 r = clk_init(pdev); 1022 if (r) 1023 dev_err(&pdev->dev, 1024 "could not register clock provider: %s: %d\n", 1025 pdev->name, r); 1026 1027 return r; 1028 } 1029 1030 static struct platform_driver clk_mt2701_drv = { 1031 .probe = clk_mt2701_probe, 1032 .driver = { 1033 .name = "clk-mt2701", 1034 .of_match_table = of_match_clk_mt2701, 1035 }, 1036 }; 1037 1038 static int __init clk_mt2701_init(void) 1039 { 1040 return platform_driver_register(&clk_mt2701_drv); 1041 } 1042 1043 arch_initcall(clk_mt2701_init); 1044