1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Shunli Wang <shunli.wang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/clk-provider.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 21 #include "clk-mtk.h" 22 #include "clk-gate.h" 23 #include "clk-cpumux.h" 24 25 #include <dt-bindings/clock/mt2701-clk.h> 26 27 /* 28 * For some clocks, we don't care what their actual rates are. And these 29 * clocks may change their rate on different products or different scenarios. 30 * So we model these clocks' rate as 0, to denote it's not an actual rate. 31 */ 32 #define DUMMY_RATE 0 33 34 static DEFINE_SPINLOCK(mt2701_clk_lock); 35 36 static const struct mtk_fixed_clk top_fixed_clks[] = { 37 FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m", 38 108 * MHZ), 39 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m", 40 400 * MHZ), 41 FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m", 42 295750000), 43 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m", 44 340 * MHZ), 45 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m", 46 340 * MHZ), 47 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m", 48 340 * MHZ), 49 FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m", 50 27 * MHZ), 51 FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m", 52 416 * MHZ), 53 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m", 54 143 * MHZ), 55 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m", 56 27 * MHZ), 57 FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m", 58 DUMMY_RATE), 59 FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m", 60 DUMMY_RATE), 61 FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m", 62 DUMMY_RATE), 63 }; 64 65 static const struct mtk_fixed_factor top_fixed_divs[] = { 66 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), 67 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 68 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 69 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 70 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 71 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 72 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 73 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 74 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 75 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 76 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 77 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8), 78 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 79 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 80 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 81 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 82 83 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1), 84 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 85 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 86 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 87 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 88 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26), 89 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52), 90 FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108), 91 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26), 92 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 93 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 94 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), 95 FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1), 96 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), 97 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), 98 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), 99 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16), 100 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32), 101 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 102 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 103 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), 104 105 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 106 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 107 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 108 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 109 110 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 111 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 112 113 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2), 114 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4), 115 FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1), 116 117 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 118 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), 119 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 120 121 FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1), 122 FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1), 123 FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2), 124 125 FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1), 126 FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2), 127 FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4), 128 129 FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1), 130 FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2), 131 FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3), 132 133 FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1), 134 135 FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1), 136 FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4), 137 FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8), 138 FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16), 139 FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24), 140 141 FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3), 142 FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3), 143 FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3), 144 FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1), 145 FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1), 146 FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8), 147 FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793), 148 FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1), 149 FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4), 150 }; 151 152 static const char * const axi_parents[] = { 153 "clk26m", 154 "syspll1_d2", 155 "syspll_d5", 156 "syspll1_d4", 157 "univpll_d5", 158 "univpll2_d2", 159 "mmpll_d2", 160 "dmpll_d2" 161 }; 162 163 static const char * const mem_parents[] = { 164 "clk26m", 165 "dmpll_ck" 166 }; 167 168 static const char * const ddrphycfg_parents[] = { 169 "clk26m", 170 "syspll1_d8" 171 }; 172 173 static const char * const mm_parents[] = { 174 "clk26m", 175 "vencpll_ck", 176 "syspll1_d2", 177 "syspll1_d4", 178 "univpll_d5", 179 "univpll1_d2", 180 "univpll2_d2", 181 "dmpll_ck" 182 }; 183 184 static const char * const pwm_parents[] = { 185 "clk26m", 186 "univpll2_d4", 187 "univpll3_d2", 188 "univpll1_d4", 189 }; 190 191 static const char * const vdec_parents[] = { 192 "clk26m", 193 "vdecpll_ck", 194 "syspll_d5", 195 "syspll1_d4", 196 "univpll_d5", 197 "univpll2_d2", 198 "vencpll_ck", 199 "msdcpll_d2", 200 "mmpll_d2" 201 }; 202 203 static const char * const mfg_parents[] = { 204 "clk26m", 205 "mmpll_ck", 206 "dmpll_x2_ck", 207 "msdcpll_ck", 208 "clk26m", 209 "syspll_d3", 210 "univpll_d3", 211 "univpll1_d2" 212 }; 213 214 static const char * const camtg_parents[] = { 215 "clk26m", 216 "univpll_d26", 217 "univpll2_d2", 218 "syspll3_d2", 219 "syspll3_d4", 220 "msdcpll_d2", 221 "mmpll_d2" 222 }; 223 224 static const char * const uart_parents[] = { 225 "clk26m", 226 "univpll2_d8" 227 }; 228 229 static const char * const spi_parents[] = { 230 "clk26m", 231 "syspll3_d2", 232 "syspll4_d2", 233 "univpll2_d4", 234 "univpll1_d8" 235 }; 236 237 static const char * const usb20_parents[] = { 238 "clk26m", 239 "univpll1_d8", 240 "univpll3_d4" 241 }; 242 243 static const char * const msdc30_parents[] = { 244 "clk26m", 245 "msdcpll_d2", 246 "syspll2_d2", 247 "syspll1_d4", 248 "univpll1_d4", 249 "univpll2_d4" 250 }; 251 252 static const char * const aud_intbus_parents[] = { 253 "clk26m", 254 "syspll1_d4", 255 "syspll3_d2", 256 "syspll4_d2", 257 "univpll3_d2", 258 "univpll2_d4" 259 }; 260 261 static const char * const pmicspi_parents[] = { 262 "clk26m", 263 "syspll1_d8", 264 "syspll2_d4", 265 "syspll4_d2", 266 "syspll3_d4", 267 "syspll2_d8", 268 "syspll1_d16", 269 "univpll3_d4", 270 "univpll_d26", 271 "dmpll_d2", 272 "dmpll_d4" 273 }; 274 275 static const char * const scp_parents[] = { 276 "clk26m", 277 "syspll1_d8", 278 "dmpll_d2", 279 "dmpll_d4" 280 }; 281 282 static const char * const dpi0_parents[] = { 283 "clk26m", 284 "mipipll", 285 "mipipll_d2", 286 "mipipll_d4", 287 "clk26m", 288 "tvdpll_ck", 289 "tvdpll_d2", 290 "tvdpll_d4" 291 }; 292 293 static const char * const dpi1_parents[] = { 294 "clk26m", 295 "tvdpll_ck", 296 "tvdpll_d2", 297 "tvdpll_d4" 298 }; 299 300 static const char * const tve_parents[] = { 301 "clk26m", 302 "mipipll", 303 "mipipll_d2", 304 "mipipll_d4", 305 "clk26m", 306 "tvdpll_ck", 307 "tvdpll_d2", 308 "tvdpll_d4" 309 }; 310 311 static const char * const hdmi_parents[] = { 312 "clk26m", 313 "hdmipll_ck", 314 "hdmipll_d2", 315 "hdmipll_d3" 316 }; 317 318 static const char * const apll_parents[] = { 319 "clk26m", 320 "audpll", 321 "audpll_d4", 322 "audpll_d8", 323 "audpll_d16", 324 "audpll_d24", 325 "clk26m", 326 "clk26m" 327 }; 328 329 static const char * const rtc_parents[] = { 330 "32k_internal", 331 "32k_external", 332 "clk26m", 333 "univpll3_d8" 334 }; 335 336 static const char * const nfi2x_parents[] = { 337 "clk26m", 338 "syspll2_d2", 339 "syspll_d7", 340 "univpll3_d2", 341 "syspll2_d4", 342 "univpll3_d4", 343 "syspll4_d4", 344 "clk26m" 345 }; 346 347 static const char * const emmc_hclk_parents[] = { 348 "clk26m", 349 "syspll1_d2", 350 "syspll1_d4", 351 "syspll2_d2" 352 }; 353 354 static const char * const flash_parents[] = { 355 "clk26m_d8", 356 "clk26m", 357 "syspll2_d8", 358 "syspll3_d4", 359 "univpll3_d4", 360 "syspll4_d2", 361 "syspll2_d4", 362 "univpll2_d4" 363 }; 364 365 static const char * const di_parents[] = { 366 "clk26m", 367 "tvd2pll_ck", 368 "tvd2pll_d2", 369 "clk26m" 370 }; 371 372 static const char * const nr_osd_parents[] = { 373 "clk26m", 374 "vencpll_ck", 375 "syspll1_d2", 376 "syspll1_d4", 377 "univpll_d5", 378 "univpll1_d2", 379 "univpll2_d2", 380 "dmpll_ck" 381 }; 382 383 static const char * const hdmirx_bist_parents[] = { 384 "clk26m", 385 "syspll_d3", 386 "clk26m", 387 "syspll1_d16", 388 "syspll4_d2", 389 "syspll1_d4", 390 "vencpll_ck", 391 "clk26m" 392 }; 393 394 static const char * const intdir_parents[] = { 395 "clk26m", 396 "mmpll_ck", 397 "syspll_d2", 398 "univpll_d2" 399 }; 400 401 static const char * const asm_parents[] = { 402 "clk26m", 403 "univpll2_d4", 404 "univpll2_d2", 405 "syspll_d5" 406 }; 407 408 static const char * const ms_card_parents[] = { 409 "clk26m", 410 "univpll3_d8", 411 "syspll4_d4" 412 }; 413 414 static const char * const ethif_parents[] = { 415 "clk26m", 416 "syspll1_d2", 417 "syspll_d5", 418 "syspll1_d4", 419 "univpll_d5", 420 "univpll1_d2", 421 "dmpll_ck", 422 "dmpll_d2" 423 }; 424 425 static const char * const hdmirx_parents[] = { 426 "clk26m", 427 "univpll_d52" 428 }; 429 430 static const char * const cmsys_parents[] = { 431 "clk26m", 432 "syspll1_d2", 433 "univpll1_d2", 434 "univpll_d5", 435 "syspll_d5", 436 "syspll2_d2", 437 "syspll1_d4", 438 "syspll3_d2", 439 "syspll2_d4", 440 "syspll1_d8", 441 "clk26m", 442 "clk26m", 443 "clk26m", 444 "clk26m", 445 "clk26m" 446 }; 447 448 static const char * const clk_8bdac_parents[] = { 449 "32k_internal", 450 "8bdac_ck", 451 "clk26m", 452 "clk26m" 453 }; 454 455 static const char * const aud2dvd_parents[] = { 456 "a1sys_hp_ck", 457 "a2sys_hp_ck" 458 }; 459 460 static const char * const padmclk_parents[] = { 461 "clk26m", 462 "univpll_d26", 463 "univpll_d52", 464 "univpll_d108", 465 "univpll2_d8", 466 "univpll2_d16", 467 "univpll2_d32" 468 }; 469 470 static const char * const aud_mux_parents[] = { 471 "clk26m", 472 "aud1pll_98m_ck", 473 "aud2pll_90m_ck", 474 "hadds2pll_98m", 475 "audio_ext1_ck", 476 "audio_ext2_ck" 477 }; 478 479 static const char * const aud_src_parents[] = { 480 "aud_mux1_sel", 481 "aud_mux2_sel" 482 }; 483 484 static const char * const cpu_parents[] = { 485 "clk26m", 486 "armpll", 487 "mainpll", 488 "mmpll" 489 }; 490 491 static const struct mtk_composite cpu_muxes[] __initconst = { 492 MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2), 493 }; 494 495 static const struct mtk_composite top_muxes[] = { 496 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 497 0x0040, 0, 3, 7, CLK_IS_CRITICAL), 498 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 499 0x0040, 8, 1, 15, CLK_IS_CRITICAL), 500 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", 501 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL), 502 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 503 0x0040, 24, 3, 31), 504 505 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 506 0x0050, 0, 2, 7), 507 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 508 0x0050, 8, 4, 15), 509 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 510 0x0050, 16, 3, 23), 511 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 512 0x0050, 24, 3, 31), 513 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 514 0x0060, 0, 1, 7), 515 516 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents, 517 0x0060, 8, 3, 15), 518 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 519 0x0060, 16, 2, 23), 520 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 521 0x0060, 24, 3, 31), 522 523 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 524 0x0070, 0, 3, 7), 525 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 526 0x0070, 8, 3, 15), 527 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents, 528 0x0070, 16, 1, 23), 529 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 530 0x0070, 24, 3, 31), 531 532 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 533 0x0080, 0, 4, 7), 534 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 535 0x0080, 8, 2, 15), 536 MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 537 0x0080, 16, 3, 23), 538 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 539 0x0080, 24, 2, 31), 540 541 MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 542 0x0090, 0, 3, 7), 543 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 544 0x0090, 8, 2, 15), 545 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 546 0x0090, 16, 3, 23), 547 548 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 549 0x00A0, 0, 2, 7, CLK_IS_CRITICAL), 550 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 551 0x00A0, 8, 3, 15), 552 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents, 553 0x00A0, 24, 2, 31), 554 555 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 556 0x00B0, 0, 3, 7), 557 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 558 0x00B0, 8, 2, 15), 559 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents, 560 0x00B0, 16, 3, 23), 561 MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents, 562 0x00B0, 24, 3, 31), 563 564 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel", 565 hdmirx_bist_parents, 0x00C0, 0, 3, 7), 566 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 567 0x00C0, 8, 2, 15), 568 MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents, 569 0x00C0, 16, 2, 23), 570 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents, 571 0x00C0, 24, 3, 31), 572 573 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents, 574 0x00D0, 0, 2, 7), 575 MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents, 576 0x00D0, 16, 2, 23), 577 MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents, 578 0x00D0, 24, 3, 31), 579 580 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents, 581 0x00E0, 0, 1, 7), 582 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 583 0x00E0, 8, 3, 15), 584 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 585 0x00E0, 16, 4, 23), 586 587 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents, 588 0x00E0, 24, 3, 31), 589 MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents, 590 0x00F0, 0, 3, 7), 591 MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents, 592 0x00F0, 8, 2, 15), 593 MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents, 594 0x00F0, 16, 1, 23), 595 596 MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents, 597 0x0100, 0, 3), 598 599 MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents, 600 0x012c, 0, 3), 601 MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents, 602 0x012c, 3, 3), 603 MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents, 604 0x012c, 6, 3), 605 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents, 606 0x012c, 15, 1, 23), 607 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents, 608 0x012c, 16, 1, 24), 609 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents, 610 0x012c, 17, 1, 25), 611 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents, 612 0x012c, 18, 1, 26), 613 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents, 614 0x012c, 19, 1, 27), 615 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents, 616 0x012c, 20, 1, 28), 617 }; 618 619 static const struct mtk_clk_divider top_adj_divs[] = { 620 DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1", 621 0x0120, 0, 8), 622 DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2", 623 0x0120, 8, 8), 624 DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel", 625 0x0120, 16, 8), 626 DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel", 627 0x0120, 24, 8), 628 DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel", 629 0x0124, 0, 8), 630 DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel", 631 0x0124, 8, 8), 632 DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel", 633 0x0124, 16, 8), 634 DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel", 635 0x0124, 24, 8), 636 DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel", 637 0x0128, 0, 8), 638 DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel", 639 0x0128, 8, 8), 640 }; 641 642 static const struct mtk_gate_regs top_aud_cg_regs = { 643 .sta_ofs = 0x012C, 644 }; 645 646 #define GATE_TOP_AUD(_id, _name, _parent, _shift) { \ 647 .id = _id, \ 648 .name = _name, \ 649 .parent_name = _parent, \ 650 .regs = &top_aud_cg_regs, \ 651 .shift = _shift, \ 652 .ops = &mtk_clk_gate_ops_no_setclr, \ 653 } 654 655 static const struct mtk_gate top_clks[] = { 656 GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div", 657 21), 658 GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div", 659 22), 660 GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div", 661 23), 662 GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div", 663 24), 664 GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div", 665 25), 666 GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div", 667 26), 668 GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div", 669 27), 670 GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 671 28), 672 }; 673 674 static int mtk_topckgen_init(struct platform_device *pdev) 675 { 676 struct clk_onecell_data *clk_data; 677 void __iomem *base; 678 struct device_node *node = pdev->dev.of_node; 679 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 680 681 base = devm_ioremap_resource(&pdev->dev, res); 682 if (IS_ERR(base)) 683 return PTR_ERR(base); 684 685 clk_data = mtk_alloc_clk_data(CLK_TOP_NR); 686 687 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 688 clk_data); 689 690 mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), 691 clk_data); 692 693 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), 694 base, &mt2701_clk_lock, clk_data); 695 696 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 697 base, &mt2701_clk_lock, clk_data); 698 699 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 700 clk_data); 701 702 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 703 } 704 705 static const struct mtk_gate_regs infra_cg_regs = { 706 .set_ofs = 0x0040, 707 .clr_ofs = 0x0044, 708 .sta_ofs = 0x0048, 709 }; 710 711 #define GATE_ICG(_id, _name, _parent, _shift) { \ 712 .id = _id, \ 713 .name = _name, \ 714 .parent_name = _parent, \ 715 .regs = &infra_cg_regs, \ 716 .shift = _shift, \ 717 .ops = &mtk_clk_gate_ops_setclr, \ 718 } 719 720 static const struct mtk_gate infra_clks[] = { 721 GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0), 722 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1), 723 GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2), 724 GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4), 725 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5), 726 GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6), 727 GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7), 728 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), 729 GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12), 730 GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13), 731 GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14), 732 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15), 733 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), 734 GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18), 735 GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19), 736 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), 737 GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23), 738 GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24), 739 }; 740 741 static const struct mtk_fixed_factor infra_fixed_divs[] = { 742 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), 743 }; 744 745 static struct clk_onecell_data *infra_clk_data; 746 747 static void __init mtk_infrasys_init_early(struct device_node *node) 748 { 749 int r, i; 750 751 if (!infra_clk_data) { 752 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 753 754 for (i = 0; i < CLK_INFRA_NR; i++) 755 infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); 756 } 757 758 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 759 infra_clk_data); 760 761 mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), 762 infra_clk_data); 763 764 r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); 765 if (r) 766 pr_err("%s(): could not register clock provider: %d\n", 767 __func__, r); 768 } 769 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg", 770 mtk_infrasys_init_early); 771 772 static int mtk_infrasys_init(struct platform_device *pdev) 773 { 774 int r, i; 775 struct device_node *node = pdev->dev.of_node; 776 777 if (!infra_clk_data) { 778 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 779 } else { 780 for (i = 0; i < CLK_INFRA_NR; i++) { 781 if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) 782 infra_clk_data->clks[i] = ERR_PTR(-ENOENT); 783 } 784 } 785 786 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 787 infra_clk_data); 788 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 789 infra_clk_data); 790 791 r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); 792 if (r) 793 return r; 794 795 mtk_register_reset_controller(node, 2, 0x30); 796 797 return 0; 798 } 799 800 static const struct mtk_gate_regs peri0_cg_regs = { 801 .set_ofs = 0x0008, 802 .clr_ofs = 0x0010, 803 .sta_ofs = 0x0018, 804 }; 805 806 static const struct mtk_gate_regs peri1_cg_regs = { 807 .set_ofs = 0x000c, 808 .clr_ofs = 0x0014, 809 .sta_ofs = 0x001c, 810 }; 811 812 #define GATE_PERI0(_id, _name, _parent, _shift) { \ 813 .id = _id, \ 814 .name = _name, \ 815 .parent_name = _parent, \ 816 .regs = &peri0_cg_regs, \ 817 .shift = _shift, \ 818 .ops = &mtk_clk_gate_ops_setclr, \ 819 } 820 821 #define GATE_PERI1(_id, _name, _parent, _shift) { \ 822 .id = _id, \ 823 .name = _name, \ 824 .parent_name = _parent, \ 825 .regs = &peri1_cg_regs, \ 826 .shift = _shift, \ 827 .ops = &mtk_clk_gate_ops_setclr, \ 828 } 829 830 static const struct mtk_gate peri_clks[] = { 831 GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31), 832 GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30), 833 GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29), 834 GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28), 835 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27), 836 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26), 837 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25), 838 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24), 839 GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23), 840 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22), 841 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21), 842 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20), 843 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19), 844 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18), 845 GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17), 846 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16), 847 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15), 848 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14), 849 GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13), 850 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), 851 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), 852 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), 853 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), 854 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8), 855 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7), 856 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6), 857 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5), 858 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4), 859 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3), 860 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2), 861 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), 862 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0), 863 864 GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11), 865 GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10), 866 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9), 867 GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8), 868 GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7), 869 GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6), 870 GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5), 871 GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4), 872 GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3), 873 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2), 874 GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1), 875 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0), 876 }; 877 878 static const char * const uart_ck_sel_parents[] = { 879 "clk26m", 880 "uart_sel", 881 }; 882 883 static const struct mtk_composite peri_muxs[] = { 884 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 885 0x40c, 0, 1), 886 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 887 0x40c, 1, 1), 888 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 889 0x40c, 2, 1), 890 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 891 0x40c, 3, 1), 892 }; 893 894 static int mtk_pericfg_init(struct platform_device *pdev) 895 { 896 struct clk_onecell_data *clk_data; 897 void __iomem *base; 898 int r; 899 struct device_node *node = pdev->dev.of_node; 900 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 901 902 base = devm_ioremap_resource(&pdev->dev, res); 903 if (IS_ERR(base)) 904 return PTR_ERR(base); 905 906 clk_data = mtk_alloc_clk_data(CLK_PERI_NR); 907 908 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), 909 clk_data); 910 911 mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, 912 &mt2701_clk_lock, clk_data); 913 914 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 915 if (r) 916 return r; 917 918 mtk_register_reset_controller(node, 2, 0x0); 919 920 return 0; 921 } 922 923 #define MT8590_PLL_FMAX (2000 * MHZ) 924 #define CON0_MT8590_RST_BAR BIT(27) 925 926 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 927 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ 928 .id = _id, \ 929 .name = _name, \ 930 .reg = _reg, \ 931 .pwr_reg = _pwr_reg, \ 932 .en_mask = _en_mask, \ 933 .flags = _flags, \ 934 .rst_bar_mask = CON0_MT8590_RST_BAR, \ 935 .fmax = MT8590_PLL_FMAX, \ 936 .pcwbits = _pcwbits, \ 937 .pd_reg = _pd_reg, \ 938 .pd_shift = _pd_shift, \ 939 .tuner_reg = _tuner_reg, \ 940 .pcw_reg = _pcw_reg, \ 941 .pcw_shift = _pcw_shift, \ 942 } 943 944 static const struct mtk_pll_data apmixed_plls[] = { 945 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001, 946 PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0), 947 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001, 948 HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0), 949 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001, 950 HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14), 951 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0, 952 21, 0x230, 4, 0x0, 0x234, 0), 953 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 954 21, 0x240, 4, 0x0, 0x244, 0), 955 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0, 956 21, 0x250, 4, 0x0, 0x254, 0), 957 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0, 958 31, 0x270, 4, 0x0, 0x274, 0), 959 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0, 960 31, 0x280, 4, 0x0, 0x284, 0), 961 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0, 962 31, 0x290, 4, 0x0, 0x294, 0), 963 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0, 964 31, 0x2a0, 4, 0x0, 0x2a4, 0), 965 PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0, 966 31, 0x2b0, 4, 0x0, 0x2b4, 0), 967 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0, 968 31, 0x2c0, 4, 0x0, 0x2c4, 0), 969 PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0, 970 21, 0x2d0, 4, 0x0, 0x2d4, 0), 971 }; 972 973 static const struct mtk_fixed_factor apmixed_fixed_divs[] = { 974 FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1), 975 }; 976 977 static int mtk_apmixedsys_init(struct platform_device *pdev) 978 { 979 struct clk_onecell_data *clk_data; 980 struct device_node *node = pdev->dev.of_node; 981 982 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR); 983 if (!clk_data) 984 return -ENOMEM; 985 986 mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls), 987 clk_data); 988 mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs), 989 clk_data); 990 991 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 992 } 993 994 static const struct of_device_id of_match_clk_mt2701[] = { 995 { 996 .compatible = "mediatek,mt2701-topckgen", 997 .data = mtk_topckgen_init, 998 }, { 999 .compatible = "mediatek,mt2701-infracfg", 1000 .data = mtk_infrasys_init, 1001 }, { 1002 .compatible = "mediatek,mt2701-pericfg", 1003 .data = mtk_pericfg_init, 1004 }, { 1005 .compatible = "mediatek,mt2701-apmixedsys", 1006 .data = mtk_apmixedsys_init, 1007 }, { 1008 /* sentinel */ 1009 } 1010 }; 1011 1012 static int clk_mt2701_probe(struct platform_device *pdev) 1013 { 1014 int (*clk_init)(struct platform_device *); 1015 int r; 1016 1017 clk_init = of_device_get_match_data(&pdev->dev); 1018 if (!clk_init) 1019 return -EINVAL; 1020 1021 r = clk_init(pdev); 1022 if (r) 1023 dev_err(&pdev->dev, 1024 "could not register clock provider: %s: %d\n", 1025 pdev->name, r); 1026 1027 return r; 1028 } 1029 1030 static struct platform_driver clk_mt2701_drv = { 1031 .probe = clk_mt2701_probe, 1032 .driver = { 1033 .name = "clk-mt2701", 1034 .of_match_table = of_match_clk_mt2701, 1035 }, 1036 }; 1037 1038 static int __init clk_mt2701_init(void) 1039 { 1040 return platform_driver_register(&clk_mt2701_drv); 1041 } 1042 1043 arch_initcall(clk_mt2701_init); 1044