1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Shunli Wang <shunli.wang@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/platform_device.h> 9 10 #include "clk-cpumux.h" 11 #include "clk-gate.h" 12 #include "clk-mtk.h" 13 #include "clk-pll.h" 14 15 #include <dt-bindings/clock/mt2701-clk.h> 16 17 /* 18 * For some clocks, we don't care what their actual rates are. And these 19 * clocks may change their rate on different products or different scenarios. 20 * So we model these clocks' rate as 0, to denote it's not an actual rate. 21 */ 22 #define DUMMY_RATE 0 23 24 static DEFINE_SPINLOCK(mt2701_clk_lock); 25 26 static const struct mtk_fixed_clk top_fixed_clks[] = { 27 FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m", 28 108 * MHZ), 29 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m", 30 400 * MHZ), 31 FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m", 32 295750000), 33 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m", 34 340 * MHZ), 35 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m", 36 340 * MHZ), 37 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m", 38 340 * MHZ), 39 FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m", 40 27 * MHZ), 41 FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m", 42 416 * MHZ), 43 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m", 44 143 * MHZ), 45 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m", 46 27 * MHZ), 47 FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m", 48 DUMMY_RATE), 49 FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m", 50 DUMMY_RATE), 51 FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m", 52 DUMMY_RATE), 53 }; 54 55 static const struct mtk_fixed_factor top_fixed_divs[] = { 56 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), 57 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 58 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 59 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 60 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 61 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 62 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 63 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 64 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 65 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 66 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 67 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8), 68 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 69 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 70 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 71 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 72 73 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1), 74 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 75 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 76 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 77 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 78 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26), 79 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52), 80 FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108), 81 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26), 82 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 83 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 84 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), 85 FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1), 86 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), 87 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), 88 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), 89 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16), 90 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32), 91 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 92 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 93 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), 94 95 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 96 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 97 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 98 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 99 100 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 101 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 102 103 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2), 104 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4), 105 FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1), 106 107 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 108 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), 109 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 110 111 FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1), 112 FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1), 113 FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2), 114 115 FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1), 116 FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2), 117 FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4), 118 119 FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1), 120 FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2), 121 FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3), 122 123 FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1), 124 125 FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1), 126 FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4), 127 FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8), 128 FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16), 129 FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24), 130 131 FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3), 132 FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3), 133 FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3), 134 FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1), 135 FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1), 136 FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8), 137 FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793), 138 FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1), 139 FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4), 140 }; 141 142 static const char * const axi_parents[] = { 143 "clk26m", 144 "syspll1_d2", 145 "syspll_d5", 146 "syspll1_d4", 147 "univpll_d5", 148 "univpll2_d2", 149 "mmpll_d2", 150 "dmpll_d2" 151 }; 152 153 static const char * const mem_parents[] = { 154 "clk26m", 155 "dmpll_ck" 156 }; 157 158 static const char * const ddrphycfg_parents[] = { 159 "clk26m", 160 "syspll1_d8" 161 }; 162 163 static const char * const mm_parents[] = { 164 "clk26m", 165 "vencpll_ck", 166 "syspll1_d2", 167 "syspll1_d4", 168 "univpll_d5", 169 "univpll1_d2", 170 "univpll2_d2", 171 "dmpll_ck" 172 }; 173 174 static const char * const pwm_parents[] = { 175 "clk26m", 176 "univpll2_d4", 177 "univpll3_d2", 178 "univpll1_d4", 179 }; 180 181 static const char * const vdec_parents[] = { 182 "clk26m", 183 "vdecpll_ck", 184 "syspll_d5", 185 "syspll1_d4", 186 "univpll_d5", 187 "univpll2_d2", 188 "vencpll_ck", 189 "msdcpll_d2", 190 "mmpll_d2" 191 }; 192 193 static const char * const mfg_parents[] = { 194 "clk26m", 195 "mmpll_ck", 196 "dmpll_x2_ck", 197 "msdcpll_ck", 198 "clk26m", 199 "syspll_d3", 200 "univpll_d3", 201 "univpll1_d2" 202 }; 203 204 static const char * const camtg_parents[] = { 205 "clk26m", 206 "univpll_d26", 207 "univpll2_d2", 208 "syspll3_d2", 209 "syspll3_d4", 210 "msdcpll_d2", 211 "mmpll_d2" 212 }; 213 214 static const char * const uart_parents[] = { 215 "clk26m", 216 "univpll2_d8" 217 }; 218 219 static const char * const spi_parents[] = { 220 "clk26m", 221 "syspll3_d2", 222 "syspll4_d2", 223 "univpll2_d4", 224 "univpll1_d8" 225 }; 226 227 static const char * const usb20_parents[] = { 228 "clk26m", 229 "univpll1_d8", 230 "univpll3_d4" 231 }; 232 233 static const char * const msdc30_parents[] = { 234 "clk26m", 235 "msdcpll_d2", 236 "syspll2_d2", 237 "syspll1_d4", 238 "univpll1_d4", 239 "univpll2_d4" 240 }; 241 242 static const char * const aud_intbus_parents[] = { 243 "clk26m", 244 "syspll1_d4", 245 "syspll3_d2", 246 "syspll4_d2", 247 "univpll3_d2", 248 "univpll2_d4" 249 }; 250 251 static const char * const pmicspi_parents[] = { 252 "clk26m", 253 "syspll1_d8", 254 "syspll2_d4", 255 "syspll4_d2", 256 "syspll3_d4", 257 "syspll2_d8", 258 "syspll1_d16", 259 "univpll3_d4", 260 "univpll_d26", 261 "dmpll_d2", 262 "dmpll_d4" 263 }; 264 265 static const char * const scp_parents[] = { 266 "clk26m", 267 "syspll1_d8", 268 "dmpll_d2", 269 "dmpll_d4" 270 }; 271 272 static const char * const dpi0_parents[] = { 273 "clk26m", 274 "mipipll", 275 "mipipll_d2", 276 "mipipll_d4", 277 "clk26m", 278 "tvdpll_ck", 279 "tvdpll_d2", 280 "tvdpll_d4" 281 }; 282 283 static const char * const dpi1_parents[] = { 284 "clk26m", 285 "tvdpll_ck", 286 "tvdpll_d2", 287 "tvdpll_d4" 288 }; 289 290 static const char * const tve_parents[] = { 291 "clk26m", 292 "mipipll", 293 "mipipll_d2", 294 "mipipll_d4", 295 "clk26m", 296 "tvdpll_ck", 297 "tvdpll_d2", 298 "tvdpll_d4" 299 }; 300 301 static const char * const hdmi_parents[] = { 302 "clk26m", 303 "hdmipll_ck", 304 "hdmipll_d2", 305 "hdmipll_d3" 306 }; 307 308 static const char * const apll_parents[] = { 309 "clk26m", 310 "audpll", 311 "audpll_d4", 312 "audpll_d8", 313 "audpll_d16", 314 "audpll_d24", 315 "clk26m", 316 "clk26m" 317 }; 318 319 static const char * const rtc_parents[] = { 320 "32k_internal", 321 "32k_external", 322 "clk26m", 323 "univpll3_d8" 324 }; 325 326 static const char * const nfi2x_parents[] = { 327 "clk26m", 328 "syspll2_d2", 329 "syspll_d7", 330 "univpll3_d2", 331 "syspll2_d4", 332 "univpll3_d4", 333 "syspll4_d4", 334 "clk26m" 335 }; 336 337 static const char * const emmc_hclk_parents[] = { 338 "clk26m", 339 "syspll1_d2", 340 "syspll1_d4", 341 "syspll2_d2" 342 }; 343 344 static const char * const flash_parents[] = { 345 "clk26m_d8", 346 "clk26m", 347 "syspll2_d8", 348 "syspll3_d4", 349 "univpll3_d4", 350 "syspll4_d2", 351 "syspll2_d4", 352 "univpll2_d4" 353 }; 354 355 static const char * const di_parents[] = { 356 "clk26m", 357 "tvd2pll_ck", 358 "tvd2pll_d2", 359 "clk26m" 360 }; 361 362 static const char * const nr_osd_parents[] = { 363 "clk26m", 364 "vencpll_ck", 365 "syspll1_d2", 366 "syspll1_d4", 367 "univpll_d5", 368 "univpll1_d2", 369 "univpll2_d2", 370 "dmpll_ck" 371 }; 372 373 static const char * const hdmirx_bist_parents[] = { 374 "clk26m", 375 "syspll_d3", 376 "clk26m", 377 "syspll1_d16", 378 "syspll4_d2", 379 "syspll1_d4", 380 "vencpll_ck", 381 "clk26m" 382 }; 383 384 static const char * const intdir_parents[] = { 385 "clk26m", 386 "mmpll_ck", 387 "syspll_d2", 388 "univpll_d2" 389 }; 390 391 static const char * const asm_parents[] = { 392 "clk26m", 393 "univpll2_d4", 394 "univpll2_d2", 395 "syspll_d5" 396 }; 397 398 static const char * const ms_card_parents[] = { 399 "clk26m", 400 "univpll3_d8", 401 "syspll4_d4" 402 }; 403 404 static const char * const ethif_parents[] = { 405 "clk26m", 406 "syspll1_d2", 407 "syspll_d5", 408 "syspll1_d4", 409 "univpll_d5", 410 "univpll1_d2", 411 "dmpll_ck", 412 "dmpll_d2" 413 }; 414 415 static const char * const hdmirx_parents[] = { 416 "clk26m", 417 "univpll_d52" 418 }; 419 420 static const char * const cmsys_parents[] = { 421 "clk26m", 422 "syspll1_d2", 423 "univpll1_d2", 424 "univpll_d5", 425 "syspll_d5", 426 "syspll2_d2", 427 "syspll1_d4", 428 "syspll3_d2", 429 "syspll2_d4", 430 "syspll1_d8", 431 "clk26m", 432 "clk26m", 433 "clk26m", 434 "clk26m", 435 "clk26m" 436 }; 437 438 static const char * const clk_8bdac_parents[] = { 439 "32k_internal", 440 "8bdac_ck", 441 "clk26m", 442 "clk26m" 443 }; 444 445 static const char * const aud2dvd_parents[] = { 446 "a1sys_hp_ck", 447 "a2sys_hp_ck" 448 }; 449 450 static const char * const padmclk_parents[] = { 451 "clk26m", 452 "univpll_d26", 453 "univpll_d52", 454 "univpll_d108", 455 "univpll2_d8", 456 "univpll2_d16", 457 "univpll2_d32" 458 }; 459 460 static const char * const aud_mux_parents[] = { 461 "clk26m", 462 "aud1pll_98m_ck", 463 "aud2pll_90m_ck", 464 "hadds2pll_98m", 465 "audio_ext1_ck", 466 "audio_ext2_ck" 467 }; 468 469 static const char * const aud_src_parents[] = { 470 "aud_mux1_sel", 471 "aud_mux2_sel" 472 }; 473 474 static const char * const cpu_parents[] = { 475 "clk26m", 476 "armpll", 477 "mainpll", 478 "mmpll" 479 }; 480 481 static const struct mtk_composite cpu_muxes[] __initconst = { 482 MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2), 483 }; 484 485 static const struct mtk_composite top_muxes[] = { 486 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 487 0x0040, 0, 3, 7, CLK_IS_CRITICAL), 488 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 489 0x0040, 8, 1, 15, CLK_IS_CRITICAL), 490 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", 491 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL), 492 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 493 0x0040, 24, 3, 31), 494 495 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 496 0x0050, 0, 2, 7), 497 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 498 0x0050, 8, 4, 15), 499 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 500 0x0050, 16, 3, 23), 501 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 502 0x0050, 24, 3, 31), 503 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 504 0x0060, 0, 1, 7), 505 506 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents, 507 0x0060, 8, 3, 15), 508 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 509 0x0060, 16, 2, 23), 510 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 511 0x0060, 24, 3, 31), 512 513 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 514 0x0070, 0, 3, 7), 515 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 516 0x0070, 8, 3, 15), 517 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents, 518 0x0070, 16, 1, 23), 519 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 520 0x0070, 24, 3, 31), 521 522 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 523 0x0080, 0, 4, 7), 524 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 525 0x0080, 8, 2, 15), 526 MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 527 0x0080, 16, 3, 23), 528 MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 529 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST), 530 531 MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 532 0x0090, 0, 3, 7), 533 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 534 0x0090, 8, 2, 15), 535 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 536 0x0090, 16, 3, 23), 537 538 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 539 0x00A0, 0, 2, 7, CLK_IS_CRITICAL), 540 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 541 0x00A0, 8, 3, 15), 542 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents, 543 0x00A0, 24, 2, 31), 544 545 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 546 0x00B0, 0, 3, 7), 547 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 548 0x00B0, 8, 2, 15), 549 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents, 550 0x00B0, 16, 3, 23), 551 MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents, 552 0x00B0, 24, 3, 31), 553 554 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel", 555 hdmirx_bist_parents, 0x00C0, 0, 3, 7), 556 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 557 0x00C0, 8, 2, 15), 558 MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents, 559 0x00C0, 16, 2, 23), 560 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents, 561 0x00C0, 24, 3, 31), 562 563 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents, 564 0x00D0, 0, 2, 7), 565 MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents, 566 0x00D0, 16, 2, 23), 567 MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents, 568 0x00D0, 24, 3, 31), 569 570 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents, 571 0x00E0, 0, 1, 7), 572 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 573 0x00E0, 8, 3, 15), 574 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 575 0x00E0, 16, 4, 23), 576 577 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents, 578 0x00E0, 24, 3, 31), 579 MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents, 580 0x00F0, 0, 3, 7), 581 MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents, 582 0x00F0, 8, 2, 15), 583 MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents, 584 0x00F0, 16, 1, 23), 585 586 MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents, 587 0x0100, 0, 3), 588 589 MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents, 590 0x012c, 0, 3), 591 MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents, 592 0x012c, 3, 3), 593 MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents, 594 0x012c, 6, 3), 595 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents, 596 0x012c, 15, 1, 23), 597 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents, 598 0x012c, 16, 1, 24), 599 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents, 600 0x012c, 17, 1, 25), 601 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents, 602 0x012c, 18, 1, 26), 603 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents, 604 0x012c, 19, 1, 27), 605 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents, 606 0x012c, 20, 1, 28), 607 }; 608 609 static const struct mtk_clk_divider top_adj_divs[] = { 610 DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1", 611 0x0120, 0, 8), 612 DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2", 613 0x0120, 8, 8), 614 DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel", 615 0x0120, 16, 8), 616 DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel", 617 0x0120, 24, 8), 618 DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel", 619 0x0124, 0, 8), 620 DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel", 621 0x0124, 8, 8), 622 DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel", 623 0x0124, 16, 8), 624 DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel", 625 0x0124, 24, 8), 626 DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel", 627 0x0128, 0, 8), 628 DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel", 629 0x0128, 8, 8), 630 }; 631 632 static const struct mtk_gate_regs top_aud_cg_regs = { 633 .sta_ofs = 0x012C, 634 }; 635 636 #define GATE_TOP_AUD(_id, _name, _parent, _shift) \ 637 GATE_MTK(_id, _name, _parent, &top_aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 638 639 static const struct mtk_gate top_clks[] = { 640 GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div", 641 21), 642 GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div", 643 22), 644 GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div", 645 23), 646 GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div", 647 24), 648 GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div", 649 25), 650 GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div", 651 26), 652 GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div", 653 27), 654 GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 655 28), 656 }; 657 658 static int mtk_topckgen_init(struct platform_device *pdev) 659 { 660 struct clk_hw_onecell_data *clk_data; 661 void __iomem *base; 662 struct device_node *node = pdev->dev.of_node; 663 664 base = devm_platform_ioremap_resource(pdev, 0); 665 if (IS_ERR(base)) 666 return PTR_ERR(base); 667 668 clk_data = mtk_alloc_clk_data(CLK_TOP_NR); 669 if (!clk_data) 670 return -ENOMEM; 671 672 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 673 clk_data); 674 675 mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), 676 clk_data); 677 678 mtk_clk_register_composites(&pdev->dev, top_muxes, 679 ARRAY_SIZE(top_muxes), base, 680 &mt2701_clk_lock, clk_data); 681 682 mtk_clk_register_dividers(&pdev->dev, top_adj_divs, ARRAY_SIZE(top_adj_divs), 683 base, &mt2701_clk_lock, clk_data); 684 685 mtk_clk_register_gates(&pdev->dev, node, top_clks, 686 ARRAY_SIZE(top_clks), clk_data); 687 688 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 689 } 690 691 static const struct mtk_gate_regs infra_cg_regs = { 692 .set_ofs = 0x0040, 693 .clr_ofs = 0x0044, 694 .sta_ofs = 0x0048, 695 }; 696 697 #define GATE_ICG(_id, _name, _parent, _shift) \ 698 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 699 700 static const struct mtk_gate infra_clks[] = { 701 GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0), 702 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1), 703 GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2), 704 GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4), 705 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5), 706 GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6), 707 GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7), 708 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), 709 GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12), 710 GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13), 711 GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14), 712 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15), 713 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), 714 GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18), 715 GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19), 716 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), 717 GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23), 718 GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24), 719 }; 720 721 static const struct mtk_fixed_factor infra_fixed_divs[] = { 722 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), 723 }; 724 725 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; 726 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 727 728 static const struct mtk_clk_rst_desc clk_rst_desc[] = { 729 /* infrasys */ 730 { 731 .version = MTK_RST_SIMPLE, 732 .rst_bank_ofs = infrasys_rst_ofs, 733 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 734 }, 735 /* pericfg */ 736 { 737 .version = MTK_RST_SIMPLE, 738 .rst_bank_ofs = pericfg_rst_ofs, 739 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 740 }, 741 }; 742 743 static struct clk_hw_onecell_data *infra_clk_data; 744 745 static void __init mtk_infrasys_init_early(struct device_node *node) 746 { 747 int r, i; 748 749 if (!infra_clk_data) { 750 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 751 if (!infra_clk_data) 752 return; 753 754 for (i = 0; i < CLK_INFRA_NR; i++) 755 infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 756 } 757 758 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 759 infra_clk_data); 760 761 mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes), 762 infra_clk_data); 763 764 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 765 infra_clk_data); 766 if (r) 767 pr_err("%s(): could not register clock provider: %d\n", 768 __func__, r); 769 } 770 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg", 771 mtk_infrasys_init_early); 772 773 static int mtk_infrasys_init(struct platform_device *pdev) 774 { 775 int r, i; 776 struct device_node *node = pdev->dev.of_node; 777 778 if (!infra_clk_data) { 779 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 780 if (!infra_clk_data) 781 return -ENOMEM; 782 } else { 783 for (i = 0; i < CLK_INFRA_NR; i++) { 784 if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER)) 785 infra_clk_data->hws[i] = ERR_PTR(-ENOENT); 786 } 787 } 788 789 mtk_clk_register_gates(&pdev->dev, node, infra_clks, 790 ARRAY_SIZE(infra_clks), infra_clk_data); 791 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 792 infra_clk_data); 793 794 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 795 infra_clk_data); 796 if (r) 797 return r; 798 799 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); 800 801 return 0; 802 } 803 804 static const struct mtk_gate_regs peri0_cg_regs = { 805 .set_ofs = 0x0008, 806 .clr_ofs = 0x0010, 807 .sta_ofs = 0x0018, 808 }; 809 810 static const struct mtk_gate_regs peri1_cg_regs = { 811 .set_ofs = 0x000c, 812 .clr_ofs = 0x0014, 813 .sta_ofs = 0x001c, 814 }; 815 816 #define GATE_PERI0(_id, _name, _parent, _shift) \ 817 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 818 819 #define GATE_PERI1(_id, _name, _parent, _shift) \ 820 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 821 822 static const struct mtk_gate peri_clks[] = { 823 GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31), 824 GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30), 825 GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29), 826 GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28), 827 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27), 828 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26), 829 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25), 830 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24), 831 GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23), 832 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22), 833 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21), 834 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20), 835 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19), 836 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18), 837 GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17), 838 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16), 839 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15), 840 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14), 841 GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13), 842 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), 843 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), 844 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), 845 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), 846 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8), 847 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7), 848 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6), 849 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5), 850 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4), 851 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3), 852 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2), 853 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), 854 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0), 855 856 GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11), 857 GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10), 858 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9), 859 GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8), 860 GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7), 861 GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6), 862 GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5), 863 GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4), 864 GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3), 865 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2), 866 GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1), 867 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0), 868 }; 869 870 static const char * const uart_ck_sel_parents[] = { 871 "clk26m", 872 "uart_sel", 873 }; 874 875 static const struct mtk_composite peri_muxs[] = { 876 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 877 0x40c, 0, 1), 878 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 879 0x40c, 1, 1), 880 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 881 0x40c, 2, 1), 882 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 883 0x40c, 3, 1), 884 }; 885 886 static int mtk_pericfg_init(struct platform_device *pdev) 887 { 888 struct clk_hw_onecell_data *clk_data; 889 void __iomem *base; 890 int r; 891 struct device_node *node = pdev->dev.of_node; 892 893 base = devm_platform_ioremap_resource(pdev, 0); 894 if (IS_ERR(base)) 895 return PTR_ERR(base); 896 897 clk_data = mtk_alloc_clk_data(CLK_PERI_NR); 898 if (!clk_data) 899 return -ENOMEM; 900 901 mtk_clk_register_gates(&pdev->dev, node, peri_clks, 902 ARRAY_SIZE(peri_clks), clk_data); 903 904 mtk_clk_register_composites(&pdev->dev, peri_muxs, 905 ARRAY_SIZE(peri_muxs), base, 906 &mt2701_clk_lock, clk_data); 907 908 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 909 if (r) 910 return r; 911 912 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); 913 914 return 0; 915 } 916 917 #define MT8590_PLL_FMAX (2000 * MHZ) 918 #define CON0_MT8590_RST_BAR BIT(27) 919 920 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 921 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ 922 .id = _id, \ 923 .name = _name, \ 924 .reg = _reg, \ 925 .pwr_reg = _pwr_reg, \ 926 .en_mask = _en_mask, \ 927 .flags = _flags, \ 928 .rst_bar_mask = CON0_MT8590_RST_BAR, \ 929 .fmax = MT8590_PLL_FMAX, \ 930 .pcwbits = _pcwbits, \ 931 .pd_reg = _pd_reg, \ 932 .pd_shift = _pd_shift, \ 933 .tuner_reg = _tuner_reg, \ 934 .pcw_reg = _pcw_reg, \ 935 .pcw_shift = _pcw_shift, \ 936 } 937 938 static const struct mtk_pll_data apmixed_plls[] = { 939 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000, 940 PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0), 941 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000, 942 HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0), 943 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000, 944 HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14), 945 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0, 946 21, 0x230, 4, 0x0, 0x234, 0), 947 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 948 21, 0x240, 4, 0x0, 0x244, 0), 949 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0, 950 21, 0x250, 4, 0x0, 0x254, 0), 951 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0, 952 31, 0x270, 4, 0x0, 0x274, 0), 953 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0, 954 31, 0x280, 4, 0x0, 0x284, 0), 955 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0, 956 31, 0x290, 4, 0x0, 0x294, 0), 957 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0, 958 31, 0x2a0, 4, 0x0, 0x2a4, 0), 959 PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0, 960 31, 0x2b0, 4, 0x0, 0x2b4, 0), 961 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0, 962 31, 0x2c0, 4, 0x0, 0x2c4, 0), 963 PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0, 964 21, 0x2d0, 4, 0x0, 0x2d4, 0), 965 }; 966 967 static const struct mtk_fixed_factor apmixed_fixed_divs[] = { 968 FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1), 969 }; 970 971 static int mtk_apmixedsys_init(struct platform_device *pdev) 972 { 973 struct clk_hw_onecell_data *clk_data; 974 struct device_node *node = pdev->dev.of_node; 975 976 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR); 977 if (!clk_data) 978 return -ENOMEM; 979 980 mtk_clk_register_plls(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls), 981 clk_data); 982 mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs), 983 clk_data); 984 985 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 986 } 987 988 static const struct of_device_id of_match_clk_mt2701[] = { 989 { 990 .compatible = "mediatek,mt2701-topckgen", 991 .data = mtk_topckgen_init, 992 }, { 993 .compatible = "mediatek,mt2701-infracfg", 994 .data = mtk_infrasys_init, 995 }, { 996 .compatible = "mediatek,mt2701-pericfg", 997 .data = mtk_pericfg_init, 998 }, { 999 .compatible = "mediatek,mt2701-apmixedsys", 1000 .data = mtk_apmixedsys_init, 1001 }, { 1002 /* sentinel */ 1003 } 1004 }; 1005 MODULE_DEVICE_TABLE(of, of_match_clk_mt2701); 1006 1007 static int clk_mt2701_probe(struct platform_device *pdev) 1008 { 1009 int (*clk_init)(struct platform_device *); 1010 int r; 1011 1012 clk_init = of_device_get_match_data(&pdev->dev); 1013 if (!clk_init) 1014 return -EINVAL; 1015 1016 r = clk_init(pdev); 1017 if (r) 1018 dev_err(&pdev->dev, 1019 "could not register clock provider: %s: %d\n", 1020 pdev->name, r); 1021 1022 return r; 1023 } 1024 1025 static struct platform_driver clk_mt2701_drv = { 1026 .probe = clk_mt2701_probe, 1027 .driver = { 1028 .name = "clk-mt2701", 1029 .of_match_table = of_match_clk_mt2701, 1030 }, 1031 }; 1032 1033 static int __init clk_mt2701_init(void) 1034 { 1035 return platform_driver_register(&clk_mt2701_drv); 1036 } 1037 1038 arch_initcall(clk_mt2701_init); 1039 1040 MODULE_DESCRIPTION("MediaTek MT2701 main clocks driver"); 1041 MODULE_LICENSE("GPL"); 1042