1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Shunli Wang <shunli.wang@mediatek.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/platform_device.h> 9 10 #include "clk-mtk.h" 11 #include "clk-gate.h" 12 13 #include <dt-bindings/clock/mt2701-clk.h> 14 15 static const struct mtk_gate_regs bdp0_cg_regs = { 16 .set_ofs = 0x0104, 17 .clr_ofs = 0x0108, 18 .sta_ofs = 0x0100, 19 }; 20 21 static const struct mtk_gate_regs bdp1_cg_regs = { 22 .set_ofs = 0x0114, 23 .clr_ofs = 0x0118, 24 .sta_ofs = 0x0110, 25 }; 26 27 #define GATE_BDP0(_id, _name, _parent, _shift) \ 28 GATE_MTK(_id, _name, _parent, &bdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 29 30 #define GATE_BDP1(_id, _name, _parent, _shift) \ 31 GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 32 33 static const struct mtk_gate bdp_clks[] = { 34 GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0), 35 GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1), 36 GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2), 37 GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3), 38 GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4), 39 GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5), 40 GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6), 41 GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7), 42 GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8), 43 GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9), 44 GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10), 45 GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11), 46 GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12), 47 GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13), 48 GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14), 49 GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15), 50 GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16), 51 GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17), 52 GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18), 53 GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19), 54 GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20), 55 GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21), 56 GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22), 57 GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23), 58 GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24), 59 GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25), 60 GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26), 61 GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27), 62 GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28), 63 GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29), 64 GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30), 65 GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31), 66 GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0), 67 GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1), 68 GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2), 69 GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3), 70 GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4), 71 GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5), 72 GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6), 73 GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7), 74 GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8), 75 GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9), 76 GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10), 77 GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11), 78 GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12), 79 GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13), 80 GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14), 81 GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15), 82 GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16), 83 }; 84 85 static const struct mtk_clk_desc bdp_desc = { 86 .clks = bdp_clks, 87 .num_clks = ARRAY_SIZE(bdp_clks), 88 }; 89 90 static const struct of_device_id of_match_clk_mt2701_bdp[] = { 91 { 92 .compatible = "mediatek,mt2701-bdpsys", 93 .data = &bdp_desc, 94 }, { 95 /* sentinel */ 96 } 97 }; 98 MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_bdp); 99 100 static struct platform_driver clk_mt2701_bdp_drv = { 101 .probe = mtk_clk_simple_probe, 102 .remove = mtk_clk_simple_remove, 103 .driver = { 104 .name = "clk-mt2701-bdp", 105 .of_match_table = of_match_clk_mt2701_bdp, 106 }, 107 }; 108 module_platform_driver(clk_mt2701_bdp_drv); 109 110 MODULE_DESCRIPTION("MediaTek MT2701 BDP clocks driver"); 111 MODULE_LICENSE("GPL"); 112