1*c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 229136ad5SPaul Burton /* 329136ad5SPaul Burton * Ingenic JZ4780 SoC CGU driver 429136ad5SPaul Burton * 529136ad5SPaul Burton * Copyright (c) 2013-2015 Imagination Technologies 6fb615d61SPaul Burton * Author: Paul Burton <paul.burton@mips.com> 729136ad5SPaul Burton */ 829136ad5SPaul Burton 929136ad5SPaul Burton #include <linux/clk-provider.h> 1029136ad5SPaul Burton #include <linux/delay.h> 1162e59c4eSStephen Boyd #include <linux/io.h> 1229136ad5SPaul Burton #include <linux/of.h> 1329136ad5SPaul Burton #include <dt-bindings/clock/jz4780-cgu.h> 1429136ad5SPaul Burton #include "cgu.h" 1529136ad5SPaul Burton 1629136ad5SPaul Burton /* CGU register offsets */ 1729136ad5SPaul Burton #define CGU_REG_CLOCKCONTROL 0x00 1829136ad5SPaul Burton #define CGU_REG_PLLCONTROL 0x0c 1929136ad5SPaul Burton #define CGU_REG_APLL 0x10 2029136ad5SPaul Burton #define CGU_REG_MPLL 0x14 2129136ad5SPaul Burton #define CGU_REG_EPLL 0x18 2229136ad5SPaul Burton #define CGU_REG_VPLL 0x1c 2329136ad5SPaul Burton #define CGU_REG_CLKGR0 0x20 2429136ad5SPaul Burton #define CGU_REG_OPCR 0x24 2529136ad5SPaul Burton #define CGU_REG_CLKGR1 0x28 2629136ad5SPaul Burton #define CGU_REG_DDRCDR 0x2c 2729136ad5SPaul Burton #define CGU_REG_VPUCDR 0x30 2829136ad5SPaul Burton #define CGU_REG_USBPCR 0x3c 2929136ad5SPaul Burton #define CGU_REG_USBRDT 0x40 3029136ad5SPaul Burton #define CGU_REG_USBVBFIL 0x44 3129136ad5SPaul Burton #define CGU_REG_USBPCR1 0x48 3229136ad5SPaul Burton #define CGU_REG_LP0CDR 0x54 3329136ad5SPaul Burton #define CGU_REG_I2SCDR 0x60 3429136ad5SPaul Burton #define CGU_REG_LP1CDR 0x64 3529136ad5SPaul Burton #define CGU_REG_MSC0CDR 0x68 3629136ad5SPaul Burton #define CGU_REG_UHCCDR 0x6c 3729136ad5SPaul Burton #define CGU_REG_SSICDR 0x74 3829136ad5SPaul Burton #define CGU_REG_CIMCDR 0x7c 3929136ad5SPaul Burton #define CGU_REG_PCMCDR 0x84 4029136ad5SPaul Burton #define CGU_REG_GPUCDR 0x88 4129136ad5SPaul Burton #define CGU_REG_HDMICDR 0x8c 4229136ad5SPaul Burton #define CGU_REG_MSC1CDR 0xa4 4329136ad5SPaul Burton #define CGU_REG_MSC2CDR 0xa8 4429136ad5SPaul Burton #define CGU_REG_BCHCDR 0xac 4529136ad5SPaul Burton #define CGU_REG_CLOCKSTATUS 0xd4 4629136ad5SPaul Burton 4729136ad5SPaul Burton /* bits within the OPCR register */ 4829136ad5SPaul Burton #define OPCR_SPENDN0 (1 << 7) 4929136ad5SPaul Burton #define OPCR_SPENDN1 (1 << 6) 5029136ad5SPaul Burton 5129136ad5SPaul Burton /* bits within the USBPCR register */ 5229136ad5SPaul Burton #define USBPCR_USB_MODE BIT(31) 5329136ad5SPaul Burton #define USBPCR_IDPULLUP_MASK (0x3 << 28) 5429136ad5SPaul Burton #define USBPCR_COMMONONN BIT(25) 5529136ad5SPaul Burton #define USBPCR_VBUSVLDEXT BIT(24) 5629136ad5SPaul Burton #define USBPCR_VBUSVLDEXTSEL BIT(23) 5729136ad5SPaul Burton #define USBPCR_POR BIT(22) 5829136ad5SPaul Burton #define USBPCR_OTG_DISABLE BIT(20) 5929136ad5SPaul Burton #define USBPCR_COMPDISTUNE_MASK (0x7 << 17) 6029136ad5SPaul Burton #define USBPCR_OTGTUNE_MASK (0x7 << 14) 6129136ad5SPaul Burton #define USBPCR_SQRXTUNE_MASK (0x7 << 11) 6229136ad5SPaul Burton #define USBPCR_TXFSLSTUNE_MASK (0xf << 7) 6329136ad5SPaul Burton #define USBPCR_TXPREEMPHTUNE BIT(6) 6429136ad5SPaul Burton #define USBPCR_TXHSXVTUNE_MASK (0x3 << 4) 6529136ad5SPaul Burton #define USBPCR_TXVREFTUNE_MASK 0xf 6629136ad5SPaul Burton 6729136ad5SPaul Burton /* bits within the USBPCR1 register */ 6829136ad5SPaul Burton #define USBPCR1_REFCLKSEL_SHIFT 26 6929136ad5SPaul Burton #define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT) 7029136ad5SPaul Burton #define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT) 7129136ad5SPaul Burton #define USBPCR1_REFCLKDIV_SHIFT 24 7229136ad5SPaul Burton #define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT) 7329136ad5SPaul Burton #define USBPCR1_REFCLKDIV_19_2 (0x3 << USBPCR1_REFCLKDIV_SHIFT) 7429136ad5SPaul Burton #define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT) 7529136ad5SPaul Burton #define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT) 7629136ad5SPaul Burton #define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT) 7729136ad5SPaul Burton #define USBPCR1_USB_SEL BIT(28) 7829136ad5SPaul Burton #define USBPCR1_WORD_IF0 BIT(19) 7929136ad5SPaul Burton #define USBPCR1_WORD_IF1 BIT(18) 8029136ad5SPaul Burton 8129136ad5SPaul Burton /* bits within the USBRDT register */ 8229136ad5SPaul Burton #define USBRDT_VBFIL_LD_EN BIT(25) 8329136ad5SPaul Burton #define USBRDT_USBRDT_MASK 0x7fffff 8429136ad5SPaul Burton 8529136ad5SPaul Burton /* bits within the USBVBFIL register */ 8629136ad5SPaul Burton #define USBVBFIL_IDDIGFIL_SHIFT 16 8729136ad5SPaul Burton #define USBVBFIL_IDDIGFIL_MASK (0xffff << USBVBFIL_IDDIGFIL_SHIFT) 8829136ad5SPaul Burton #define USBVBFIL_USBVBFIL_MASK (0xffff) 8929136ad5SPaul Burton 9029136ad5SPaul Burton static struct ingenic_cgu *cgu; 9129136ad5SPaul Burton 9229136ad5SPaul Burton static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw) 9329136ad5SPaul Burton { 9429136ad5SPaul Burton /* we only use CLKCORE, revisit if that ever changes */ 9529136ad5SPaul Burton return 0; 9629136ad5SPaul Burton } 9729136ad5SPaul Burton 9829136ad5SPaul Burton static int jz4780_otg_phy_set_parent(struct clk_hw *hw, u8 idx) 9929136ad5SPaul Burton { 10029136ad5SPaul Burton unsigned long flags; 10129136ad5SPaul Burton u32 usbpcr1; 10229136ad5SPaul Burton 10329136ad5SPaul Burton if (idx > 0) 10429136ad5SPaul Burton return -EINVAL; 10529136ad5SPaul Burton 10629136ad5SPaul Burton spin_lock_irqsave(&cgu->lock, flags); 10729136ad5SPaul Burton 10829136ad5SPaul Burton usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); 10929136ad5SPaul Burton usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK; 11029136ad5SPaul Burton /* we only use CLKCORE */ 11129136ad5SPaul Burton usbpcr1 |= USBPCR1_REFCLKSEL_CORE; 11229136ad5SPaul Burton writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); 11329136ad5SPaul Burton 11429136ad5SPaul Burton spin_unlock_irqrestore(&cgu->lock, flags); 11529136ad5SPaul Burton return 0; 11629136ad5SPaul Burton } 11729136ad5SPaul Burton 11829136ad5SPaul Burton static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw, 11929136ad5SPaul Burton unsigned long parent_rate) 12029136ad5SPaul Burton { 12129136ad5SPaul Burton u32 usbpcr1; 12229136ad5SPaul Burton unsigned refclk_div; 12329136ad5SPaul Burton 12429136ad5SPaul Burton usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); 12529136ad5SPaul Burton refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK; 12629136ad5SPaul Burton 12729136ad5SPaul Burton switch (refclk_div) { 12829136ad5SPaul Burton case USBPCR1_REFCLKDIV_12: 12929136ad5SPaul Burton return 12000000; 13029136ad5SPaul Burton 13129136ad5SPaul Burton case USBPCR1_REFCLKDIV_24: 13229136ad5SPaul Burton return 24000000; 13329136ad5SPaul Burton 13429136ad5SPaul Burton case USBPCR1_REFCLKDIV_48: 13529136ad5SPaul Burton return 48000000; 13629136ad5SPaul Burton 13729136ad5SPaul Burton case USBPCR1_REFCLKDIV_19_2: 13829136ad5SPaul Burton return 19200000; 13929136ad5SPaul Burton } 14029136ad5SPaul Burton 14129136ad5SPaul Burton BUG(); 14229136ad5SPaul Burton return parent_rate; 14329136ad5SPaul Burton } 14429136ad5SPaul Burton 14529136ad5SPaul Burton static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate, 14629136ad5SPaul Burton unsigned long *parent_rate) 14729136ad5SPaul Burton { 14829136ad5SPaul Burton if (req_rate < 15600000) 14929136ad5SPaul Burton return 12000000; 15029136ad5SPaul Burton 15129136ad5SPaul Burton if (req_rate < 21600000) 15229136ad5SPaul Burton return 19200000; 15329136ad5SPaul Burton 15429136ad5SPaul Burton if (req_rate < 36000000) 15529136ad5SPaul Burton return 24000000; 15629136ad5SPaul Burton 15729136ad5SPaul Burton return 48000000; 15829136ad5SPaul Burton } 15929136ad5SPaul Burton 16029136ad5SPaul Burton static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, 16129136ad5SPaul Burton unsigned long parent_rate) 16229136ad5SPaul Burton { 16329136ad5SPaul Burton unsigned long flags; 16429136ad5SPaul Burton u32 usbpcr1, div_bits; 16529136ad5SPaul Burton 16629136ad5SPaul Burton switch (req_rate) { 16729136ad5SPaul Burton case 12000000: 16829136ad5SPaul Burton div_bits = USBPCR1_REFCLKDIV_12; 16929136ad5SPaul Burton break; 17029136ad5SPaul Burton 17129136ad5SPaul Burton case 19200000: 17229136ad5SPaul Burton div_bits = USBPCR1_REFCLKDIV_19_2; 17329136ad5SPaul Burton break; 17429136ad5SPaul Burton 17529136ad5SPaul Burton case 24000000: 17629136ad5SPaul Burton div_bits = USBPCR1_REFCLKDIV_24; 17729136ad5SPaul Burton break; 17829136ad5SPaul Burton 17929136ad5SPaul Burton case 48000000: 18029136ad5SPaul Burton div_bits = USBPCR1_REFCLKDIV_48; 18129136ad5SPaul Burton break; 18229136ad5SPaul Burton 18329136ad5SPaul Burton default: 18429136ad5SPaul Burton return -EINVAL; 18529136ad5SPaul Burton } 18629136ad5SPaul Burton 18729136ad5SPaul Burton spin_lock_irqsave(&cgu->lock, flags); 18829136ad5SPaul Burton 18929136ad5SPaul Burton usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); 19029136ad5SPaul Burton usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK; 19129136ad5SPaul Burton usbpcr1 |= div_bits; 19229136ad5SPaul Burton writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); 19329136ad5SPaul Burton 19429136ad5SPaul Burton spin_unlock_irqrestore(&cgu->lock, flags); 19529136ad5SPaul Burton return 0; 19629136ad5SPaul Burton } 19729136ad5SPaul Burton 198ee1f9df2SPaul Cercueil static const struct clk_ops jz4780_otg_phy_ops = { 19929136ad5SPaul Burton .get_parent = jz4780_otg_phy_get_parent, 20029136ad5SPaul Burton .set_parent = jz4780_otg_phy_set_parent, 20129136ad5SPaul Burton 20229136ad5SPaul Burton .recalc_rate = jz4780_otg_phy_recalc_rate, 20329136ad5SPaul Burton .round_rate = jz4780_otg_phy_round_rate, 20429136ad5SPaul Burton .set_rate = jz4780_otg_phy_set_rate, 20529136ad5SPaul Burton }; 20629136ad5SPaul Burton 20729136ad5SPaul Burton static const s8 pll_od_encoding[16] = { 20829136ad5SPaul Burton 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 20929136ad5SPaul Burton 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 21029136ad5SPaul Burton }; 21129136ad5SPaul Burton 21229136ad5SPaul Burton static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { 21329136ad5SPaul Burton 21429136ad5SPaul Burton /* External clocks */ 21529136ad5SPaul Burton 21629136ad5SPaul Burton [JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, 21729136ad5SPaul Burton [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, 21829136ad5SPaul Burton 21929136ad5SPaul Burton /* PLLs */ 22029136ad5SPaul Burton 22129136ad5SPaul Burton #define DEF_PLL(name) { \ 22229136ad5SPaul Burton .reg = CGU_REG_ ## name, \ 22329136ad5SPaul Burton .m_shift = 19, \ 22429136ad5SPaul Burton .m_bits = 13, \ 22529136ad5SPaul Burton .m_offset = 1, \ 22629136ad5SPaul Burton .n_shift = 13, \ 22729136ad5SPaul Burton .n_bits = 6, \ 22829136ad5SPaul Burton .n_offset = 1, \ 22929136ad5SPaul Burton .od_shift = 9, \ 23029136ad5SPaul Burton .od_bits = 4, \ 23129136ad5SPaul Burton .od_max = 16, \ 23229136ad5SPaul Burton .od_encoding = pll_od_encoding, \ 23329136ad5SPaul Burton .stable_bit = 6, \ 23429136ad5SPaul Burton .bypass_bit = 1, \ 23529136ad5SPaul Burton .enable_bit = 0, \ 23629136ad5SPaul Burton } 23729136ad5SPaul Burton 23829136ad5SPaul Burton [JZ4780_CLK_APLL] = { 23929136ad5SPaul Burton "apll", CGU_CLK_PLL, 24029136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 24129136ad5SPaul Burton .pll = DEF_PLL(APLL), 24229136ad5SPaul Burton }, 24329136ad5SPaul Burton 24429136ad5SPaul Burton [JZ4780_CLK_MPLL] = { 24529136ad5SPaul Burton "mpll", CGU_CLK_PLL, 24629136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 24729136ad5SPaul Burton .pll = DEF_PLL(MPLL), 24829136ad5SPaul Burton }, 24929136ad5SPaul Burton 25029136ad5SPaul Burton [JZ4780_CLK_EPLL] = { 25129136ad5SPaul Burton "epll", CGU_CLK_PLL, 25229136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 25329136ad5SPaul Burton .pll = DEF_PLL(EPLL), 25429136ad5SPaul Burton }, 25529136ad5SPaul Burton 25629136ad5SPaul Burton [JZ4780_CLK_VPLL] = { 25729136ad5SPaul Burton "vpll", CGU_CLK_PLL, 25829136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 25929136ad5SPaul Burton .pll = DEF_PLL(VPLL), 26029136ad5SPaul Burton }, 26129136ad5SPaul Burton 26229136ad5SPaul Burton #undef DEF_PLL 26329136ad5SPaul Burton 26429136ad5SPaul Burton /* Custom (SoC-specific) OTG PHY */ 26529136ad5SPaul Burton 26629136ad5SPaul Burton [JZ4780_CLK_OTGPHY] = { 26729136ad5SPaul Burton "otg_phy", CGU_CLK_CUSTOM, 26829136ad5SPaul Burton .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 }, 26929136ad5SPaul Burton .custom = { &jz4780_otg_phy_ops }, 27029136ad5SPaul Burton }, 27129136ad5SPaul Burton 27229136ad5SPaul Burton /* Muxes & dividers */ 27329136ad5SPaul Burton 27429136ad5SPaul Burton [JZ4780_CLK_SCLKA] = { 27529136ad5SPaul Burton "sclk_a", CGU_CLK_MUX, 27629136ad5SPaul Burton .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK, 27729136ad5SPaul Burton JZ4780_CLK_RTCLK }, 27829136ad5SPaul Burton .mux = { CGU_REG_CLOCKCONTROL, 30, 2 }, 27929136ad5SPaul Burton }, 28029136ad5SPaul Burton 28129136ad5SPaul Burton [JZ4780_CLK_CPUMUX] = { 28229136ad5SPaul Burton "cpumux", CGU_CLK_MUX, 28329136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 28429136ad5SPaul Burton JZ4780_CLK_EPLL }, 28529136ad5SPaul Burton .mux = { CGU_REG_CLOCKCONTROL, 28, 2 }, 28629136ad5SPaul Burton }, 28729136ad5SPaul Burton 28829136ad5SPaul Burton [JZ4780_CLK_CPU] = { 28929136ad5SPaul Burton "cpu", CGU_CLK_DIV, 29029136ad5SPaul Burton .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, 2914afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 }, 29229136ad5SPaul Burton }, 29329136ad5SPaul Burton 29429136ad5SPaul Burton [JZ4780_CLK_L2CACHE] = { 29529136ad5SPaul Burton "l2cache", CGU_CLK_DIV, 29629136ad5SPaul Burton .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, 2974afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 }, 29829136ad5SPaul Burton }, 29929136ad5SPaul Burton 30029136ad5SPaul Burton [JZ4780_CLK_AHB0] = { 30129136ad5SPaul Burton "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, 30229136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 30329136ad5SPaul Burton JZ4780_CLK_EPLL }, 30429136ad5SPaul Burton .mux = { CGU_REG_CLOCKCONTROL, 26, 2 }, 3054afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 }, 30629136ad5SPaul Burton }, 30729136ad5SPaul Burton 30829136ad5SPaul Burton [JZ4780_CLK_AHB2PMUX] = { 30929136ad5SPaul Burton "ahb2_apb_mux", CGU_CLK_MUX, 31029136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 31129136ad5SPaul Burton JZ4780_CLK_RTCLK }, 31229136ad5SPaul Burton .mux = { CGU_REG_CLOCKCONTROL, 24, 2 }, 31329136ad5SPaul Burton }, 31429136ad5SPaul Burton 31529136ad5SPaul Burton [JZ4780_CLK_AHB2] = { 31629136ad5SPaul Burton "ahb2", CGU_CLK_DIV, 31729136ad5SPaul Burton .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, 3184afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 }, 31929136ad5SPaul Burton }, 32029136ad5SPaul Burton 32129136ad5SPaul Burton [JZ4780_CLK_PCLK] = { 32229136ad5SPaul Burton "pclk", CGU_CLK_DIV, 32329136ad5SPaul Burton .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, 3244afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 }, 32529136ad5SPaul Burton }, 32629136ad5SPaul Burton 32729136ad5SPaul Burton [JZ4780_CLK_DDR] = { 32829136ad5SPaul Burton "ddr", CGU_CLK_MUX | CGU_CLK_DIV, 32929136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, 33029136ad5SPaul Burton .mux = { CGU_REG_DDRCDR, 30, 2 }, 3314afe2d1aSHarvey Hunt .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, 33229136ad5SPaul Burton }, 33329136ad5SPaul Burton 33429136ad5SPaul Burton [JZ4780_CLK_VPU] = { 33529136ad5SPaul Burton "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 33629136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 33729136ad5SPaul Burton JZ4780_CLK_EPLL, -1 }, 33829136ad5SPaul Burton .mux = { CGU_REG_VPUCDR, 30, 2 }, 3394afe2d1aSHarvey Hunt .div = { CGU_REG_VPUCDR, 0, 1, 4, 29, 28, 27 }, 34029136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 2 }, 34129136ad5SPaul Burton }, 34229136ad5SPaul Burton 34329136ad5SPaul Burton [JZ4780_CLK_I2SPLL] = { 34429136ad5SPaul Burton "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV, 34529136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 }, 34629136ad5SPaul Burton .mux = { CGU_REG_I2SCDR, 30, 1 }, 3474afe2d1aSHarvey Hunt .div = { CGU_REG_I2SCDR, 0, 1, 8, 29, 28, 27 }, 34829136ad5SPaul Burton }, 34929136ad5SPaul Burton 35029136ad5SPaul Burton [JZ4780_CLK_I2S] = { 35129136ad5SPaul Burton "i2s", CGU_CLK_MUX, 35229136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 }, 35329136ad5SPaul Burton .mux = { CGU_REG_I2SCDR, 31, 1 }, 35429136ad5SPaul Burton }, 35529136ad5SPaul Burton 35629136ad5SPaul Burton [JZ4780_CLK_LCD0PIXCLK] = { 35729136ad5SPaul Burton "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV, 35829136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 35929136ad5SPaul Burton JZ4780_CLK_VPLL, -1 }, 36029136ad5SPaul Burton .mux = { CGU_REG_LP0CDR, 30, 2 }, 3614afe2d1aSHarvey Hunt .div = { CGU_REG_LP0CDR, 0, 1, 8, 28, 27, 26 }, 36229136ad5SPaul Burton }, 36329136ad5SPaul Burton 36429136ad5SPaul Burton [JZ4780_CLK_LCD1PIXCLK] = { 36529136ad5SPaul Burton "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV, 36629136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 36729136ad5SPaul Burton JZ4780_CLK_VPLL, -1 }, 36829136ad5SPaul Burton .mux = { CGU_REG_LP1CDR, 30, 2 }, 3694afe2d1aSHarvey Hunt .div = { CGU_REG_LP1CDR, 0, 1, 8, 28, 27, 26 }, 37029136ad5SPaul Burton }, 37129136ad5SPaul Burton 37229136ad5SPaul Burton [JZ4780_CLK_MSCMUX] = { 37329136ad5SPaul Burton "msc_mux", CGU_CLK_MUX, 37429136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, 37529136ad5SPaul Burton .mux = { CGU_REG_MSC0CDR, 30, 2 }, 37629136ad5SPaul Burton }, 37729136ad5SPaul Burton 37829136ad5SPaul Burton [JZ4780_CLK_MSC0] = { 37929136ad5SPaul Burton "msc0", CGU_CLK_DIV | CGU_CLK_GATE, 38029136ad5SPaul Burton .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, 3814afe2d1aSHarvey Hunt .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, 38229136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 3 }, 38329136ad5SPaul Burton }, 38429136ad5SPaul Burton 38529136ad5SPaul Burton [JZ4780_CLK_MSC1] = { 38629136ad5SPaul Burton "msc1", CGU_CLK_DIV | CGU_CLK_GATE, 38729136ad5SPaul Burton .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, 3884afe2d1aSHarvey Hunt .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, 38929136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 11 }, 39029136ad5SPaul Burton }, 39129136ad5SPaul Burton 39229136ad5SPaul Burton [JZ4780_CLK_MSC2] = { 39329136ad5SPaul Burton "msc2", CGU_CLK_DIV | CGU_CLK_GATE, 39429136ad5SPaul Burton .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, 3954afe2d1aSHarvey Hunt .div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 }, 39629136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 12 }, 39729136ad5SPaul Burton }, 39829136ad5SPaul Burton 39929136ad5SPaul Burton [JZ4780_CLK_UHC] = { 40029136ad5SPaul Burton "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 40129136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 40229136ad5SPaul Burton JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY }, 40329136ad5SPaul Burton .mux = { CGU_REG_UHCCDR, 30, 2 }, 4044afe2d1aSHarvey Hunt .div = { CGU_REG_UHCCDR, 0, 1, 8, 29, 28, 27 }, 40529136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 24 }, 40629136ad5SPaul Burton }, 40729136ad5SPaul Burton 40829136ad5SPaul Burton [JZ4780_CLK_SSIPLL] = { 40929136ad5SPaul Burton "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, 41029136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, 41129136ad5SPaul Burton .mux = { CGU_REG_SSICDR, 30, 1 }, 4124afe2d1aSHarvey Hunt .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, 41329136ad5SPaul Burton }, 41429136ad5SPaul Burton 41529136ad5SPaul Burton [JZ4780_CLK_SSI] = { 41629136ad5SPaul Burton "ssi", CGU_CLK_MUX, 41729136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 }, 41829136ad5SPaul Burton .mux = { CGU_REG_SSICDR, 31, 1 }, 41929136ad5SPaul Burton }, 42029136ad5SPaul Burton 42129136ad5SPaul Burton [JZ4780_CLK_CIMMCLK] = { 42229136ad5SPaul Burton "cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV, 42329136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, 42429136ad5SPaul Burton .mux = { CGU_REG_CIMCDR, 31, 1 }, 4254afe2d1aSHarvey Hunt .div = { CGU_REG_CIMCDR, 0, 1, 8, 30, 29, 28 }, 42629136ad5SPaul Burton }, 42729136ad5SPaul Burton 42829136ad5SPaul Burton [JZ4780_CLK_PCMPLL] = { 42929136ad5SPaul Burton "pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV, 43029136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 43129136ad5SPaul Burton JZ4780_CLK_EPLL, JZ4780_CLK_VPLL }, 43229136ad5SPaul Burton .mux = { CGU_REG_PCMCDR, 29, 2 }, 4334afe2d1aSHarvey Hunt .div = { CGU_REG_PCMCDR, 0, 1, 8, 28, 27, 26 }, 43429136ad5SPaul Burton }, 43529136ad5SPaul Burton 43629136ad5SPaul Burton [JZ4780_CLK_PCM] = { 43729136ad5SPaul Burton "pcm", CGU_CLK_MUX | CGU_CLK_GATE, 43829136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 }, 43929136ad5SPaul Burton .mux = { CGU_REG_PCMCDR, 31, 1 }, 44029136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 3 }, 44129136ad5SPaul Burton }, 44229136ad5SPaul Burton 44329136ad5SPaul Burton [JZ4780_CLK_GPU] = { 44429136ad5SPaul Burton "gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 44529136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 44629136ad5SPaul Burton JZ4780_CLK_EPLL }, 44729136ad5SPaul Burton .mux = { CGU_REG_GPUCDR, 30, 2 }, 4484afe2d1aSHarvey Hunt .div = { CGU_REG_GPUCDR, 0, 1, 4, 29, 28, 27 }, 44929136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 4 }, 45029136ad5SPaul Burton }, 45129136ad5SPaul Burton 45229136ad5SPaul Burton [JZ4780_CLK_HDMI] = { 45329136ad5SPaul Burton "hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 45429136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 45529136ad5SPaul Burton JZ4780_CLK_VPLL, -1 }, 45629136ad5SPaul Burton .mux = { CGU_REG_HDMICDR, 30, 2 }, 4574afe2d1aSHarvey Hunt .div = { CGU_REG_HDMICDR, 0, 1, 8, 29, 28, 26 }, 45829136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 9 }, 45929136ad5SPaul Burton }, 46029136ad5SPaul Burton 46129136ad5SPaul Burton [JZ4780_CLK_BCH] = { 46229136ad5SPaul Burton "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 46329136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, 46429136ad5SPaul Burton JZ4780_CLK_EPLL }, 46529136ad5SPaul Burton .mux = { CGU_REG_BCHCDR, 30, 2 }, 4664afe2d1aSHarvey Hunt .div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 }, 46729136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 1 }, 46829136ad5SPaul Burton }, 46929136ad5SPaul Burton 47029136ad5SPaul Burton /* Gate-only clocks */ 47129136ad5SPaul Burton 47229136ad5SPaul Burton [JZ4780_CLK_NEMC] = { 47329136ad5SPaul Burton "nemc", CGU_CLK_GATE, 47429136ad5SPaul Burton .parents = { JZ4780_CLK_AHB2, -1, -1, -1 }, 47529136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 0 }, 47629136ad5SPaul Burton }, 47729136ad5SPaul Burton 47829136ad5SPaul Burton [JZ4780_CLK_OTG0] = { 47929136ad5SPaul Burton "otg0", CGU_CLK_GATE, 48029136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 48129136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 2 }, 48229136ad5SPaul Burton }, 48329136ad5SPaul Burton 48429136ad5SPaul Burton [JZ4780_CLK_SSI0] = { 48529136ad5SPaul Burton "ssi0", CGU_CLK_GATE, 48629136ad5SPaul Burton .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, 48729136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 4 }, 48829136ad5SPaul Burton }, 48929136ad5SPaul Burton 49029136ad5SPaul Burton [JZ4780_CLK_SMB0] = { 49129136ad5SPaul Burton "smb0", CGU_CLK_GATE, 49229136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 49329136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 5 }, 49429136ad5SPaul Burton }, 49529136ad5SPaul Burton 49629136ad5SPaul Burton [JZ4780_CLK_SMB1] = { 49729136ad5SPaul Burton "smb1", CGU_CLK_GATE, 49829136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 49929136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 6 }, 50029136ad5SPaul Burton }, 50129136ad5SPaul Burton 50229136ad5SPaul Burton [JZ4780_CLK_SCC] = { 50329136ad5SPaul Burton "scc", CGU_CLK_GATE, 50429136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 50529136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 7 }, 50629136ad5SPaul Burton }, 50729136ad5SPaul Burton 50829136ad5SPaul Burton [JZ4780_CLK_AIC] = { 50929136ad5SPaul Burton "aic", CGU_CLK_GATE, 51029136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 51129136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 8 }, 51229136ad5SPaul Burton }, 51329136ad5SPaul Burton 51429136ad5SPaul Burton [JZ4780_CLK_TSSI0] = { 51529136ad5SPaul Burton "tssi0", CGU_CLK_GATE, 51629136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 51729136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 9 }, 51829136ad5SPaul Burton }, 51929136ad5SPaul Burton 52029136ad5SPaul Burton [JZ4780_CLK_OWI] = { 52129136ad5SPaul Burton "owi", CGU_CLK_GATE, 52229136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 52329136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 10 }, 52429136ad5SPaul Burton }, 52529136ad5SPaul Burton 52629136ad5SPaul Burton [JZ4780_CLK_KBC] = { 52729136ad5SPaul Burton "kbc", CGU_CLK_GATE, 52829136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 52929136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 13 }, 53029136ad5SPaul Burton }, 53129136ad5SPaul Burton 53229136ad5SPaul Burton [JZ4780_CLK_SADC] = { 53329136ad5SPaul Burton "sadc", CGU_CLK_GATE, 53429136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 53529136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 14 }, 53629136ad5SPaul Burton }, 53729136ad5SPaul Burton 53829136ad5SPaul Burton [JZ4780_CLK_UART0] = { 53929136ad5SPaul Burton "uart0", CGU_CLK_GATE, 54029136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 54129136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 15 }, 54229136ad5SPaul Burton }, 54329136ad5SPaul Burton 54429136ad5SPaul Burton [JZ4780_CLK_UART1] = { 54529136ad5SPaul Burton "uart1", CGU_CLK_GATE, 54629136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 54729136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 16 }, 54829136ad5SPaul Burton }, 54929136ad5SPaul Burton 55029136ad5SPaul Burton [JZ4780_CLK_UART2] = { 55129136ad5SPaul Burton "uart2", CGU_CLK_GATE, 55229136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 55329136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 17 }, 55429136ad5SPaul Burton }, 55529136ad5SPaul Burton 55629136ad5SPaul Burton [JZ4780_CLK_UART3] = { 55729136ad5SPaul Burton "uart3", CGU_CLK_GATE, 55829136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 55929136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 18 }, 56029136ad5SPaul Burton }, 56129136ad5SPaul Burton 56229136ad5SPaul Burton [JZ4780_CLK_SSI1] = { 56329136ad5SPaul Burton "ssi1", CGU_CLK_GATE, 56429136ad5SPaul Burton .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, 56529136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 19 }, 56629136ad5SPaul Burton }, 56729136ad5SPaul Burton 56829136ad5SPaul Burton [JZ4780_CLK_SSI2] = { 56929136ad5SPaul Burton "ssi2", CGU_CLK_GATE, 57029136ad5SPaul Burton .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, 57129136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 20 }, 57229136ad5SPaul Burton }, 57329136ad5SPaul Burton 57429136ad5SPaul Burton [JZ4780_CLK_PDMA] = { 57529136ad5SPaul Burton "pdma", CGU_CLK_GATE, 57629136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 57729136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 21 }, 57829136ad5SPaul Burton }, 57929136ad5SPaul Burton 58029136ad5SPaul Burton [JZ4780_CLK_GPS] = { 58129136ad5SPaul Burton "gps", CGU_CLK_GATE, 58229136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 58329136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 22 }, 58429136ad5SPaul Burton }, 58529136ad5SPaul Burton 58629136ad5SPaul Burton [JZ4780_CLK_MAC] = { 58729136ad5SPaul Burton "mac", CGU_CLK_GATE, 58829136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 58929136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 23 }, 59029136ad5SPaul Burton }, 59129136ad5SPaul Burton 59229136ad5SPaul Burton [JZ4780_CLK_SMB2] = { 59329136ad5SPaul Burton "smb2", CGU_CLK_GATE, 59429136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 59529136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 24 }, 59629136ad5SPaul Burton }, 59729136ad5SPaul Burton 59829136ad5SPaul Burton [JZ4780_CLK_CIM] = { 59929136ad5SPaul Burton "cim", CGU_CLK_GATE, 60029136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 60129136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 26 }, 60229136ad5SPaul Burton }, 60329136ad5SPaul Burton 60429136ad5SPaul Burton [JZ4780_CLK_LCD] = { 60529136ad5SPaul Burton "lcd", CGU_CLK_GATE, 60629136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 60729136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 28 }, 60829136ad5SPaul Burton }, 60929136ad5SPaul Burton 61029136ad5SPaul Burton [JZ4780_CLK_TVE] = { 61129136ad5SPaul Burton "tve", CGU_CLK_GATE, 61229136ad5SPaul Burton .parents = { JZ4780_CLK_LCD, -1, -1, -1 }, 61329136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 27 }, 61429136ad5SPaul Burton }, 61529136ad5SPaul Burton 61629136ad5SPaul Burton [JZ4780_CLK_IPU] = { 61729136ad5SPaul Burton "ipu", CGU_CLK_GATE, 61829136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 61929136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 29 }, 62029136ad5SPaul Burton }, 62129136ad5SPaul Burton 62229136ad5SPaul Burton [JZ4780_CLK_DDR0] = { 62329136ad5SPaul Burton "ddr0", CGU_CLK_GATE, 62429136ad5SPaul Burton .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, 62529136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 30 }, 62629136ad5SPaul Burton }, 62729136ad5SPaul Burton 62829136ad5SPaul Burton [JZ4780_CLK_DDR1] = { 62929136ad5SPaul Burton "ddr1", CGU_CLK_GATE, 63029136ad5SPaul Burton .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, 63129136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 31 }, 63229136ad5SPaul Burton }, 63329136ad5SPaul Burton 63429136ad5SPaul Burton [JZ4780_CLK_SMB3] = { 63529136ad5SPaul Burton "smb3", CGU_CLK_GATE, 63629136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 63729136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 0 }, 63829136ad5SPaul Burton }, 63929136ad5SPaul Burton 64029136ad5SPaul Burton [JZ4780_CLK_TSSI1] = { 64129136ad5SPaul Burton "tssi1", CGU_CLK_GATE, 64229136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 64329136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 1 }, 64429136ad5SPaul Burton }, 64529136ad5SPaul Burton 64629136ad5SPaul Burton [JZ4780_CLK_COMPRESS] = { 64729136ad5SPaul Burton "compress", CGU_CLK_GATE, 64829136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 64929136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 5 }, 65029136ad5SPaul Burton }, 65129136ad5SPaul Burton 65229136ad5SPaul Burton [JZ4780_CLK_AIC1] = { 65329136ad5SPaul Burton "aic1", CGU_CLK_GATE, 65429136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 65529136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 6 }, 65629136ad5SPaul Burton }, 65729136ad5SPaul Burton 65829136ad5SPaul Burton [JZ4780_CLK_GPVLC] = { 65929136ad5SPaul Burton "gpvlc", CGU_CLK_GATE, 66029136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 66129136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 7 }, 66229136ad5SPaul Burton }, 66329136ad5SPaul Burton 66429136ad5SPaul Burton [JZ4780_CLK_OTG1] = { 66529136ad5SPaul Burton "otg1", CGU_CLK_GATE, 66629136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 66729136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 8 }, 66829136ad5SPaul Burton }, 66929136ad5SPaul Burton 67029136ad5SPaul Burton [JZ4780_CLK_UART4] = { 67129136ad5SPaul Burton "uart4", CGU_CLK_GATE, 67229136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 67329136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 10 }, 67429136ad5SPaul Burton }, 67529136ad5SPaul Burton 67629136ad5SPaul Burton [JZ4780_CLK_AHBMON] = { 67729136ad5SPaul Burton "ahb_mon", CGU_CLK_GATE, 67829136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 67929136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 11 }, 68029136ad5SPaul Burton }, 68129136ad5SPaul Burton 68229136ad5SPaul Burton [JZ4780_CLK_SMB4] = { 68329136ad5SPaul Burton "smb4", CGU_CLK_GATE, 68429136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, 68529136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 12 }, 68629136ad5SPaul Burton }, 68729136ad5SPaul Burton 68829136ad5SPaul Burton [JZ4780_CLK_DES] = { 68929136ad5SPaul Burton "des", CGU_CLK_GATE, 69029136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 69129136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 13 }, 69229136ad5SPaul Burton }, 69329136ad5SPaul Burton 69429136ad5SPaul Burton [JZ4780_CLK_X2D] = { 69529136ad5SPaul Burton "x2d", CGU_CLK_GATE, 69629136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, 69729136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 14 }, 69829136ad5SPaul Burton }, 69929136ad5SPaul Burton 70029136ad5SPaul Burton [JZ4780_CLK_CORE1] = { 70129136ad5SPaul Burton "core1", CGU_CLK_GATE, 70229136ad5SPaul Burton .parents = { JZ4780_CLK_CPU, -1, -1, -1 }, 70329136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 15 }, 70429136ad5SPaul Burton }, 70529136ad5SPaul Burton 70629136ad5SPaul Burton }; 70729136ad5SPaul Burton 70829136ad5SPaul Burton static void __init jz4780_cgu_init(struct device_node *np) 70929136ad5SPaul Burton { 71029136ad5SPaul Burton int retval; 71129136ad5SPaul Burton 71229136ad5SPaul Burton cgu = ingenic_cgu_new(jz4780_cgu_clocks, 71329136ad5SPaul Burton ARRAY_SIZE(jz4780_cgu_clocks), np); 71429136ad5SPaul Burton if (!cgu) { 71529136ad5SPaul Burton pr_err("%s: failed to initialise CGU\n", __func__); 71629136ad5SPaul Burton return; 71729136ad5SPaul Burton } 71829136ad5SPaul Burton 71929136ad5SPaul Burton retval = ingenic_cgu_register_clocks(cgu); 72029136ad5SPaul Burton if (retval) { 72129136ad5SPaul Burton pr_err("%s: failed to register CGU Clocks\n", __func__); 72229136ad5SPaul Burton return; 72329136ad5SPaul Burton } 72429136ad5SPaul Burton } 72529136ad5SPaul Burton CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); 726