1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __MACH_IMX_CLK_H 3 #define __MACH_IMX_CLK_H 4 5 #include <linux/spinlock.h> 6 #include <linux/clk-provider.h> 7 8 extern spinlock_t imx_ccm_lock; 9 10 void imx_check_clocks(struct clk *clks[], unsigned int count); 11 void imx_register_uart_clocks(struct clk ** const clks[]); 12 13 extern void imx_cscmr1_fixup(u32 *val); 14 15 enum imx_pllv1_type { 16 IMX_PLLV1_IMX1, 17 IMX_PLLV1_IMX21, 18 IMX_PLLV1_IMX25, 19 IMX_PLLV1_IMX27, 20 IMX_PLLV1_IMX31, 21 IMX_PLLV1_IMX35, 22 }; 23 24 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, 25 const char *parent, void __iomem *base); 26 27 struct clk *imx_clk_pllv2(const char *name, const char *parent, 28 void __iomem *base); 29 30 enum imx_pllv3_type { 31 IMX_PLLV3_GENERIC, 32 IMX_PLLV3_SYS, 33 IMX_PLLV3_USB, 34 IMX_PLLV3_USB_VF610, 35 IMX_PLLV3_AV, 36 IMX_PLLV3_ENET, 37 IMX_PLLV3_ENET_IMX7, 38 IMX_PLLV3_SYS_VF610, 39 IMX_PLLV3_DDR_IMX7, 40 }; 41 42 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 43 const char *parent_name, void __iomem *base, u32 div_mask); 44 45 struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name, 46 void __iomem *base); 47 48 struct clk *clk_register_gate2(struct device *dev, const char *name, 49 const char *parent_name, unsigned long flags, 50 void __iomem *reg, u8 bit_idx, u8 cgr_val, 51 u8 clk_gate_flags, spinlock_t *lock, 52 unsigned int *share_count); 53 54 struct clk * imx_obtain_fixed_clock( 55 const char *name, unsigned long rate); 56 57 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, 58 void __iomem *reg, u8 shift, u32 exclusive_mask); 59 60 struct clk *imx_clk_pfd(const char *name, const char *parent_name, 61 void __iomem *reg, u8 idx); 62 63 struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name, 64 void __iomem *reg, u8 idx); 65 66 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, 67 void __iomem *reg, u8 shift, u8 width, 68 void __iomem *busy_reg, u8 busy_shift); 69 70 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, 71 u8 width, void __iomem *busy_reg, u8 busy_shift, 72 const char **parent_names, int num_parents); 73 74 struct clk *imx_clk_fixup_divider(const char *name, const char *parent, 75 void __iomem *reg, u8 shift, u8 width, 76 void (*fixup)(u32 *val)); 77 78 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, 79 u8 shift, u8 width, const char **parents, 80 int num_parents, void (*fixup)(u32 *val)); 81 82 static inline struct clk *imx_clk_fixed(const char *name, int rate) 83 { 84 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 85 } 86 87 static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, 88 u8 shift, u8 width, const char **parents, int num_parents) 89 { 90 return clk_register_mux(NULL, name, parents, num_parents, 91 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, 92 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); 93 } 94 95 static inline struct clk *imx_clk_fixed_factor(const char *name, 96 const char *parent, unsigned int mult, unsigned int div) 97 { 98 return clk_register_fixed_factor(NULL, name, parent, 99 CLK_SET_RATE_PARENT, mult, div); 100 } 101 102 static inline struct clk *imx_clk_divider(const char *name, const char *parent, 103 void __iomem *reg, u8 shift, u8 width) 104 { 105 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, 106 reg, shift, width, 0, &imx_ccm_lock); 107 } 108 109 static inline struct clk *imx_clk_divider_flags(const char *name, 110 const char *parent, void __iomem *reg, u8 shift, u8 width, 111 unsigned long flags) 112 { 113 return clk_register_divider(NULL, name, parent, flags, 114 reg, shift, width, 0, &imx_ccm_lock); 115 } 116 117 static inline struct clk *imx_clk_divider2(const char *name, const char *parent, 118 void __iomem *reg, u8 shift, u8 width) 119 { 120 return clk_register_divider(NULL, name, parent, 121 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 122 reg, shift, width, 0, &imx_ccm_lock); 123 } 124 125 static inline struct clk *imx_clk_gate(const char *name, const char *parent, 126 void __iomem *reg, u8 shift) 127 { 128 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 129 shift, 0, &imx_ccm_lock); 130 } 131 132 static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent, 133 void __iomem *reg, u8 shift, unsigned long flags) 134 { 135 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 136 shift, 0, &imx_ccm_lock); 137 } 138 139 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, 140 void __iomem *reg, u8 shift) 141 { 142 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 143 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 144 } 145 146 static inline struct clk *imx_clk_gate_dis_flags(const char *name, const char *parent, 147 void __iomem *reg, u8 shift, unsigned long flags) 148 { 149 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 150 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 151 } 152 153 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 154 void __iomem *reg, u8 shift) 155 { 156 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 157 shift, 0x3, 0, &imx_ccm_lock, NULL); 158 } 159 160 static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent, 161 void __iomem *reg, u8 shift, unsigned long flags) 162 { 163 return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 164 shift, 0x3, 0, &imx_ccm_lock, NULL); 165 } 166 167 static inline struct clk *imx_clk_gate2_shared(const char *name, 168 const char *parent, void __iomem *reg, u8 shift, 169 unsigned int *share_count) 170 { 171 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 172 shift, 0x3, 0, &imx_ccm_lock, share_count); 173 } 174 175 static inline struct clk *imx_clk_gate2_shared2(const char *name, 176 const char *parent, void __iomem *reg, u8 shift, 177 unsigned int *share_count) 178 { 179 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | 180 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, 181 &imx_ccm_lock, share_count); 182 } 183 184 static inline struct clk *imx_clk_gate2_cgr(const char *name, 185 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) 186 { 187 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 188 shift, cgr_val, 0, &imx_ccm_lock, NULL); 189 } 190 191 static inline struct clk *imx_clk_gate3(const char *name, const char *parent, 192 void __iomem *reg, u8 shift) 193 { 194 return clk_register_gate(NULL, name, parent, 195 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 196 reg, shift, 0, &imx_ccm_lock); 197 } 198 199 static inline struct clk *imx_clk_gate4(const char *name, const char *parent, 200 void __iomem *reg, u8 shift) 201 { 202 return clk_register_gate2(NULL, name, parent, 203 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 204 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 205 } 206 207 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, 208 u8 shift, u8 width, const char **parents, int num_parents) 209 { 210 return clk_register_mux(NULL, name, parents, num_parents, 211 CLK_SET_RATE_NO_REPARENT, reg, shift, 212 width, 0, &imx_ccm_lock); 213 } 214 215 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, 216 u8 shift, u8 width, const char **parents, int num_parents) 217 { 218 return clk_register_mux(NULL, name, parents, num_parents, 219 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 220 reg, shift, width, 0, &imx_ccm_lock); 221 } 222 223 static inline struct clk *imx_clk_mux_flags(const char *name, 224 void __iomem *reg, u8 shift, u8 width, const char **parents, 225 int num_parents, unsigned long flags) 226 { 227 return clk_register_mux(NULL, name, parents, num_parents, 228 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, 229 &imx_ccm_lock); 230 } 231 232 struct clk *imx_clk_cpu(const char *name, const char *parent_name, 233 struct clk *div, struct clk *mux, struct clk *pll, 234 struct clk *step); 235 236 struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name, 237 unsigned long flags, void __iomem *reg, u8 shift, u8 width, 238 u8 clk_divider_flags, const struct clk_div_table *table, 239 spinlock_t *lock); 240 #endif 241