1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __MACH_IMX_CLK_H 3 #define __MACH_IMX_CLK_H 4 5 #include <linux/spinlock.h> 6 #include <linux/clk-provider.h> 7 8 extern spinlock_t imx_ccm_lock; 9 10 void imx_check_clocks(struct clk *clks[], unsigned int count); 11 void imx_register_uart_clocks(struct clk ** const clks[]); 12 13 extern void imx_cscmr1_fixup(u32 *val); 14 15 enum imx_pllv1_type { 16 IMX_PLLV1_IMX1, 17 IMX_PLLV1_IMX21, 18 IMX_PLLV1_IMX25, 19 IMX_PLLV1_IMX27, 20 IMX_PLLV1_IMX31, 21 IMX_PLLV1_IMX35, 22 }; 23 24 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, 25 const char *parent, void __iomem *base); 26 27 struct clk *imx_clk_pllv2(const char *name, const char *parent, 28 void __iomem *base); 29 30 enum imx_pllv3_type { 31 IMX_PLLV3_GENERIC, 32 IMX_PLLV3_SYS, 33 IMX_PLLV3_USB, 34 IMX_PLLV3_USB_VF610, 35 IMX_PLLV3_AV, 36 IMX_PLLV3_ENET, 37 IMX_PLLV3_ENET_IMX7, 38 IMX_PLLV3_SYS_VF610, 39 IMX_PLLV3_DDR_IMX7, 40 }; 41 42 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 43 const char *parent_name, void __iomem *base, u32 div_mask); 44 45 struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name, 46 void __iomem *base); 47 48 struct clk *clk_register_gate2(struct device *dev, const char *name, 49 const char *parent_name, unsigned long flags, 50 void __iomem *reg, u8 bit_idx, u8 cgr_val, 51 u8 clk_gate_flags, spinlock_t *lock, 52 unsigned int *share_count); 53 54 struct clk * imx_obtain_fixed_clock( 55 const char *name, unsigned long rate); 56 57 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, 58 void __iomem *reg, u8 shift, u32 exclusive_mask); 59 60 struct clk *imx_clk_pfd(const char *name, const char *parent_name, 61 void __iomem *reg, u8 idx); 62 63 struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name, 64 void __iomem *reg, u8 idx); 65 66 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, 67 void __iomem *reg, u8 shift, u8 width, 68 void __iomem *busy_reg, u8 busy_shift); 69 70 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, 71 u8 width, void __iomem *busy_reg, u8 busy_shift, 72 const char **parent_names, int num_parents); 73 74 struct clk_hw *imx7ulp_clk_composite(const char *name, 75 const char * const *parent_names, 76 int num_parents, bool mux_present, 77 bool rate_present, bool gate_present, 78 void __iomem *reg); 79 80 struct clk *imx_clk_fixup_divider(const char *name, const char *parent, 81 void __iomem *reg, u8 shift, u8 width, 82 void (*fixup)(u32 *val)); 83 84 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, 85 u8 shift, u8 width, const char **parents, 86 int num_parents, void (*fixup)(u32 *val)); 87 88 static inline struct clk *imx_clk_fixed(const char *name, int rate) 89 { 90 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 91 } 92 93 static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, 94 u8 shift, u8 width, const char **parents, int num_parents) 95 { 96 return clk_register_mux(NULL, name, parents, num_parents, 97 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, 98 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); 99 } 100 101 static inline struct clk *imx_clk_fixed_factor(const char *name, 102 const char *parent, unsigned int mult, unsigned int div) 103 { 104 return clk_register_fixed_factor(NULL, name, parent, 105 CLK_SET_RATE_PARENT, mult, div); 106 } 107 108 static inline struct clk *imx_clk_divider(const char *name, const char *parent, 109 void __iomem *reg, u8 shift, u8 width) 110 { 111 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, 112 reg, shift, width, 0, &imx_ccm_lock); 113 } 114 115 static inline struct clk *imx_clk_divider_flags(const char *name, 116 const char *parent, void __iomem *reg, u8 shift, u8 width, 117 unsigned long flags) 118 { 119 return clk_register_divider(NULL, name, parent, flags, 120 reg, shift, width, 0, &imx_ccm_lock); 121 } 122 123 static inline struct clk *imx_clk_divider2(const char *name, const char *parent, 124 void __iomem *reg, u8 shift, u8 width) 125 { 126 return clk_register_divider(NULL, name, parent, 127 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 128 reg, shift, width, 0, &imx_ccm_lock); 129 } 130 131 static inline struct clk *imx_clk_gate(const char *name, const char *parent, 132 void __iomem *reg, u8 shift) 133 { 134 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 135 shift, 0, &imx_ccm_lock); 136 } 137 138 static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent, 139 void __iomem *reg, u8 shift, unsigned long flags) 140 { 141 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 142 shift, 0, &imx_ccm_lock); 143 } 144 145 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, 146 void __iomem *reg, u8 shift) 147 { 148 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 149 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 150 } 151 152 static inline struct clk *imx_clk_gate_dis_flags(const char *name, const char *parent, 153 void __iomem *reg, u8 shift, unsigned long flags) 154 { 155 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 156 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 157 } 158 159 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 160 void __iomem *reg, u8 shift) 161 { 162 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 163 shift, 0x3, 0, &imx_ccm_lock, NULL); 164 } 165 166 static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent, 167 void __iomem *reg, u8 shift, unsigned long flags) 168 { 169 return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 170 shift, 0x3, 0, &imx_ccm_lock, NULL); 171 } 172 173 static inline struct clk *imx_clk_gate2_shared(const char *name, 174 const char *parent, void __iomem *reg, u8 shift, 175 unsigned int *share_count) 176 { 177 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 178 shift, 0x3, 0, &imx_ccm_lock, share_count); 179 } 180 181 static inline struct clk *imx_clk_gate2_shared2(const char *name, 182 const char *parent, void __iomem *reg, u8 shift, 183 unsigned int *share_count) 184 { 185 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | 186 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, 187 &imx_ccm_lock, share_count); 188 } 189 190 static inline struct clk *imx_clk_gate2_cgr(const char *name, 191 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) 192 { 193 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 194 shift, cgr_val, 0, &imx_ccm_lock, NULL); 195 } 196 197 static inline struct clk *imx_clk_gate3(const char *name, const char *parent, 198 void __iomem *reg, u8 shift) 199 { 200 return clk_register_gate(NULL, name, parent, 201 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 202 reg, shift, 0, &imx_ccm_lock); 203 } 204 205 static inline struct clk *imx_clk_gate4(const char *name, const char *parent, 206 void __iomem *reg, u8 shift) 207 { 208 return clk_register_gate2(NULL, name, parent, 209 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 210 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 211 } 212 213 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, 214 u8 shift, u8 width, const char **parents, int num_parents) 215 { 216 return clk_register_mux(NULL, name, parents, num_parents, 217 CLK_SET_RATE_NO_REPARENT, reg, shift, 218 width, 0, &imx_ccm_lock); 219 } 220 221 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, 222 u8 shift, u8 width, const char **parents, int num_parents) 223 { 224 return clk_register_mux(NULL, name, parents, num_parents, 225 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 226 reg, shift, width, 0, &imx_ccm_lock); 227 } 228 229 static inline struct clk *imx_clk_mux_flags(const char *name, 230 void __iomem *reg, u8 shift, u8 width, const char **parents, 231 int num_parents, unsigned long flags) 232 { 233 return clk_register_mux(NULL, name, parents, num_parents, 234 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, 235 &imx_ccm_lock); 236 } 237 238 struct clk *imx_clk_cpu(const char *name, const char *parent_name, 239 struct clk *div, struct clk *mux, struct clk *pll, 240 struct clk *step); 241 242 struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name, 243 unsigned long flags, void __iomem *reg, u8 shift, u8 width, 244 u8 clk_divider_flags, const struct clk_div_table *table, 245 spinlock_t *lock); 246 #endif 247